1 files changed, 287 insertions, 0 deletions
diff --git a/constraints/constraints.srcs/constrs_2/imports/kintex7/top_full.xdc b/constraints/constraints.srcs/constrs_2/imports/kintex7/top_full.xdc
new file mode 100644
index 0000000..c92dd3a
--- /dev/null
+++ b/constraints/constraints.srcs/constrs_2/imports/kintex7/top_full.xdc
@@ -0,0 +1,287 @@
+# Define the top level system clock of the design
+create_clock -period 10 -name sysClk [get_ports sysClk]
+
+# Define the clocks for the GTX blocks
+create_clock -name gt0_txusrclk_i -period 12.8 [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt0_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -name gt2_txusrclk_i -period 12.8 [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt2_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -name gt4_txusrclk_i -period 12.8 [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt4_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+create_clock -name gt6_txusrclk_i -period 12.8 [get_pins mgtEngine/ROCKETIO_WRAPPER_TILE_i/gt6_ROCKETIO_WRAPPER_TILE_i/gtxe2_i/TXOUTCLK]
+
+
+# IO delays
+set_input_delay -clock sysClk 0.0 [get_ports or1200_clmode]
+set_input_delay -clock sysClk 0.0 [get_ports or1200_pic_ints]
+set_input_delay -clock sysClk 3.0 [get_ports DataIn_pad_0_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports LineState_pad_0_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports RxActive_pad_0_i]
+set_input_delay -clock sysClk 3.0 [get_ports RxError_pad_0_i]
+set_input_delay -clock sysClk 3.0 [get_ports RxValid_pad_0_i]
+set_input_delay -clock sysClk 3.0 [get_ports TxReady_pad_0_i]
+set_input_delay -clock sysClk 3.0 [get_ports VStatus_pad_0_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports usb_vbus_pad_0_i]
+set_input_delay -clock sysClk 3.0 [get_ports DataIn_pad_1_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports LineState_pad_1_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports RxActive_pad_1_i]
+set_input_delay -clock sysClk 3.0 [get_ports RxError_pad_1_i]
+set_input_delay -clock sysClk 3.0 [get_ports RxValid_pad_1_i]
+set_input_delay -clock sysClk 3.0 [get_ports TxReady_pad_1_i]
+set_input_delay -clock sysClk 3.0 [get_ports VStatus_pad_1_i[*]]
+set_input_delay -clock sysClk 3.0 [get_ports usb_vbus_pad_1_i]
+set_input_delay -clock sysClk 0.0 [get_ports reset]
+
+set_output_delay -clock sysClk 0.0 [get_ports or1200_pm_out[*]]
+set_output_delay -clock sysClk 0.0 [get_ports TermSel_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports TxValid_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports VControl_Load_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports XcvSelect_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports TermSel_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports TxValid_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports VControl_Load_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports XcvSelect_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports OpMode_pad_0_o[*]]
+set_output_delay -clock sysClk 0.0 [get_ports OpMode_pad_1_o[*]]
+set_output_delay -clock sysClk 0.0 [get_ports SuspendM_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports SuspendM_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports VControl_pad_0_o[*]]
+set_output_delay -clock sysClk 0.0 [get_ports VControl_pad_1_o[*]]
+set_output_delay -clock sysClk 0.0 [get_ports phy_rst_pad_0_o]
+set_output_delay -clock sysClk 0.0 [get_ports phy_rst_pad_1_o]
+set_output_delay -clock sysClk 0.0 [get_ports DataOut_pad_0_o[*]]
+set_output_delay -clock sysClk 0.0 [get_ports DataOut_pad_1_o[*]]
+
+# Timing exceptions
+set_false_path -from [get_ports GTPRESET_IN]
+
+# Multi-cycle paths for ALU
+set_multicycle_path -through [get_pins cpuEngine/or1200_cpu/or1200_alu/*] 2
+set_multicycle_path -hold -through [get_pins cpuEngine/or1200_cpu/or1200_alu/*] 1
+
+# I/O Constraints
+set_property IOSTANDARD LVCMOS18 [get_ports sysClk]
+set_property IOSTANDARD LVCMOS18 [get_ports reset]
+set_property IOSTANDARD LVCMOS18 [get_ports phy_rst_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TxValid_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TxReady_pad_0_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxValid_pad_0_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxActive_pad_0_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxError_pad_0_i]
+set_property IOSTANDARD LVCMOS18 [get_ports XcvSelect_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TermSel_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports SuspendM_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports usb_vbus_pad_0_i]
+set_property IOSTANDARD LVCMOS18 [get_ports VControl_Load_pad_0_o]
+set_property IOSTANDARD LVCMOS18 [get_ports phy_rst_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TxValid_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TxReady_pad_1_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxValid_pad_1_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxActive_pad_1_i]
+set_property IOSTANDARD LVCMOS18 [get_ports RxError_pad_1_i]
+set_property IOSTANDARD LVCMOS18 [get_ports XcvSelect_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports TermSel_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports SuspendM_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports usb_vbus_pad_1_i]
+set_property IOSTANDARD LVCMOS18 [get_ports VControl_Load_pad_1_o]
+set_property IOSTANDARD LVCMOS18 [get_ports or1200_clmode]
+set_property IOSTANDARD LVCMOS18 [get_ports or1200_pic_ints]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_0_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_0_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LineState_pad_0_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LineState_pad_0_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OpMode_pad_0_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OpMode_pad_0_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_0_o[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_0_o[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_0_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_0_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_0_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataOut_pad_1_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DataIn_pad_1_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LineState_pad_1_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LineState_pad_1_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OpMode_pad_1_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OpMode_pad_1_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_1_o[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_1_o[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_1_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VControl_pad_1_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {VStatus_pad_1_i[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {or1200_pm_out[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {or1200_pm_out[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {or1200_pm_out[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {or1200_pm_out[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports GTPRESET_IN]
+set_property PACKAGE_PIN G24 [get_ports {DataIn_pad_0_i[0]}]
+set_property PACKAGE_PIN F24 [get_ports {DataIn_pad_0_i[1]}]
+set_property PACKAGE_PIN G22 [get_ports {DataIn_pad_0_i[2]}]
+set_property PACKAGE_PIN F23 [get_ports {DataIn_pad_0_i[3]}]
+set_property PACKAGE_PIN F22 [get_ports {DataIn_pad_0_i[4]}]
+set_property PACKAGE_PIN E23 [get_ports {DataIn_pad_0_i[5]}]
+set_property PACKAGE_PIN D23 [get_ports {DataIn_pad_0_i[6]}]
+set_property PACKAGE_PIN D24 [get_ports {DataIn_pad_0_i[7]}]
+set_property PACKAGE_PIN K18 [get_ports {DataIn_pad_1_i[0]}]
+set_property PACKAGE_PIN L17 [get_ports {DataIn_pad_1_i[1]}]
+set_property PACKAGE_PIN L18 [get_ports {DataIn_pad_1_i[2]}]
+set_property PACKAGE_PIN M17 [get_ports {DataIn_pad_1_i[3]}]
+set_property PACKAGE_PIN K17 [get_ports {DataIn_pad_1_i[4]}]
+set_property PACKAGE_PIN K16 [get_ports {DataIn_pad_1_i[5]}]
+set_property PACKAGE_PIN L20 [get_ports {DataIn_pad_1_i[6]}]
+set_property PACKAGE_PIN L19 [get_ports {DataIn_pad_1_i[7]}]
+set_property PACKAGE_PIN C21 [get_ports {DataOut_pad_0_o[0]}]
+set_property PACKAGE_PIN B21 [get_ports {DataOut_pad_0_o[1]}]
+set_property PACKAGE_PIN E21 [get_ports {DataOut_pad_0_o[2]}]
+set_property PACKAGE_PIN E22 [get_ports {DataOut_pad_0_o[3]}]
+set_property PACKAGE_PIN B20 [get_ports {DataOut_pad_0_o[4]}]
+set_property PACKAGE_PIN A20 [get_ports {DataOut_pad_0_o[5]}]
+set_property PACKAGE_PIN D21 [get_ports {DataOut_pad_0_o[6]}]
+set_property PACKAGE_PIN C22 [get_ports {DataOut_pad_0_o[7]}]
+set_property PACKAGE_PIN J19 [get_ports {DataOut_pad_1_o[0]}]
+set_property PACKAGE_PIN J18 [get_ports {DataOut_pad_1_o[1]}]
+set_property PACKAGE_PIN J20 [get_ports {DataOut_pad_1_o[2]}]
+set_property PACKAGE_PIN K20 [get_ports {DataOut_pad_1_o[3]}]
+set_property PACKAGE_PIN G20 [get_ports {DataOut_pad_1_o[4]}]
+set_property PACKAGE_PIN H19 [get_ports {DataOut_pad_1_o[5]}]
+set_property PACKAGE_PIN E20 [get_ports {DataOut_pad_1_o[6]}]
+set_property PACKAGE_PIN F19 [get_ports {DataOut_pad_1_o[7]}]
+set_property PACKAGE_PIN Y8 [get_ports GTPRESET_IN]
+set_property PACKAGE_PIN C23 [get_ports {LineState_pad_0_i[0]}]
+set_property PACKAGE_PIN C24 [get_ports {LineState_pad_0_i[1]}]
+set_property PACKAGE_PIN F20 [get_ports {LineState_pad_1_i[0]}]
+set_property PACKAGE_PIN G19 [get_ports {LineState_pad_1_i[1]}]
+set_property PACKAGE_PIN D26 [get_ports {OpMode_pad_0_o[0]}]
+set_property PACKAGE_PIN C26 [get_ports {OpMode_pad_0_o[1]}]
+set_property PACKAGE_PIN D20 [get_ports {OpMode_pad_1_o[0]}]
+set_property PACKAGE_PIN D19 [get_ports {OpMode_pad_1_o[1]}]
+set_property PACKAGE_PIN D1 [get_ports {TXN_OUT[0]}]
+set_property PACKAGE_PIN D2 [get_ports {TXP_OUT[0]}]
+set_property PACKAGE_PIN E4 [get_ports {RXP_IN[0]}]
+set_property PACKAGE_PIN E3 [get_ports {RXN_IN[0]}]
+set_property PACKAGE_PIN B1 [get_ports {TXN_OUT[1]}]
+set_property PACKAGE_PIN B2 [get_ports {TXP_OUT[1]}]
+set_property PACKAGE_PIN C4 [get_ports {RXP_IN[1]}]
+set_property PACKAGE_PIN C3 [get_ports {RXN_IN[1]}]
+set_property PACKAGE_PIN F1 [get_ports {TXN_OUT[2]}]
+set_property PACKAGE_PIN F2 [get_ports {TXP_OUT[2]}]
+set_property PACKAGE_PIN G4 [get_ports {RXP_IN[2]}]
+set_property PACKAGE_PIN G3 [get_ports {RXN_IN[2]}]
+set_property PACKAGE_PIN H1 [get_ports {TXN_OUT[3]}]
+set_property PACKAGE_PIN H2 [get_ports {TXP_OUT[3]}]
+set_property PACKAGE_PIN J4 [get_ports {RXP_IN[3]}]
+set_property PACKAGE_PIN J3 [get_ports {RXN_IN[3]}]
+set_property PACKAGE_PIN K1 [get_ports {TXN_OUT[4]}]
+set_property PACKAGE_PIN K2 [get_ports {TXP_OUT[4]}]
+set_property PACKAGE_PIN L4 [get_ports {RXP_IN[4]}]
+set_property PACKAGE_PIN L3 [get_ports {RXN_IN[4]}]
+set_property PACKAGE_PIN M1 [get_ports {TXN_OUT[5]}]
+set_property PACKAGE_PIN M2 [get_ports {TXP_OUT[5]}]
+set_property PACKAGE_PIN N4 [get_ports {RXP_IN[5]}]
+set_property PACKAGE_PIN N3 [get_ports {RXN_IN[5]}]
+set_property PACKAGE_PIN R4 [get_ports {RXP_IN[6]}]
+set_property PACKAGE_PIN P1 [get_ports {TXN_OUT[6]}]
+set_property PACKAGE_PIN P2 [get_ports {TXP_OUT[6]}]
+set_property PACKAGE_PIN R3 [get_ports {RXN_IN[6]}]
+set_property PACKAGE_PIN B5 [get_ports {RXN_IN[7]}]
+set_property PACKAGE_PIN A3 [get_ports {TXN_OUT[7]}]
+set_property PACKAGE_PIN A4 [get_ports {TXP_OUT[7]}]
+set_property PACKAGE_PIN B6 [get_ports {RXP_IN[7]}]
+set_property PACKAGE_PIN E26 [get_ports RxActive_pad_0_i]
+set_property PACKAGE_PIN G15 [get_ports RxActive_pad_1_i]
+set_property PACKAGE_PIN F25 [get_ports RxError_pad_0_i]
+set_property PACKAGE_PIN G16 [get_ports RxError_pad_1_i]
+set_property PACKAGE_PIN H26 [get_ports RxValid_pad_0_i]
+set_property PACKAGE_PIN H16 [get_ports RxValid_pad_1_i]
+set_property PACKAGE_PIN J26 [get_ports SuspendM_pad_0_o]
+set_property PACKAGE_PIN D16 [get_ports SuspendM_pad_1_o]
+set_property PACKAGE_PIN G21 [get_ports TermSel_pad_0_o]
+set_property PACKAGE_PIN D15 [get_ports TermSel_pad_1_o]
+set_property PACKAGE_PIN H21 [get_ports TxReady_pad_0_i]
+set_property PACKAGE_PIN C18 [get_ports TxReady_pad_1_i]
+set_property PACKAGE_PIN H24 [get_ports TxValid_pad_0_o]
+set_property PACKAGE_PIN C17 [get_ports TxValid_pad_1_o]
+set_property PACKAGE_PIN H22 [get_ports VControl_Load_pad_0_o]
+set_property PACKAGE_PIN C19 [get_ports VControl_Load_pad_1_o]
+set_property PACKAGE_PIN A23 [get_ports {VControl_pad_0_o[0]}]
+set_property PACKAGE_PIN A24 [get_ports {VControl_pad_0_o[1]}]
+set_property PACKAGE_PIN B25 [get_ports {VControl_pad_0_o[2]}]
+set_property PACKAGE_PIN B26 [get_ports {VControl_pad_0_o[3]}]
+set_property PACKAGE_PIN H18 [get_ports {VControl_pad_1_o[0]}]
+set_property PACKAGE_PIN H17 [get_ports {VControl_pad_1_o[1]}]
+set_property PACKAGE_PIN D18 [get_ports {VControl_pad_1_o[2]}]
+set_property PACKAGE_PIN E18 [get_ports {VControl_pad_1_o[3]}]
+set_property PACKAGE_PIN B22 [get_ports {VStatus_pad_0_i[0]}]
+set_property PACKAGE_PIN A22 [get_ports {VStatus_pad_0_i[1]}]
+set_property PACKAGE_PIN B24 [get_ports {VStatus_pad_0_i[2]}]
+set_property PACKAGE_PIN A25 [get_ports {VStatus_pad_0_i[3]}]
+set_property PACKAGE_PIN K21 [get_ports {VStatus_pad_0_i[4]}]
+set_property PACKAGE_PIN D25 [get_ports {VStatus_pad_0_i[5]}]
+set_property PACKAGE_PIN E25 [get_ports {VStatus_pad_0_i[6]}]
+set_property PACKAGE_PIN G26 [get_ports {VStatus_pad_0_i[7]}]
+set_property PACKAGE_PIN E17 [get_ports {VStatus_pad_1_i[0]}]
+set_property PACKAGE_PIN F17 [get_ports {VStatus_pad_1_i[1]}]
+set_property PACKAGE_PIN F18 [get_ports {VStatus_pad_1_i[2]}]
+set_property PACKAGE_PIN G17 [get_ports {VStatus_pad_1_i[3]}]
+set_property PACKAGE_PIN E16 [get_ports {VStatus_pad_1_i[4]}]
+set_property PACKAGE_PIN E15 [get_ports {VStatus_pad_1_i[5]}]
+set_property PACKAGE_PIN J16 [get_ports {VStatus_pad_1_i[6]}]
+set_property PACKAGE_PIN J15 [get_ports {VStatus_pad_1_i[7]}]
+set_property PACKAGE_PIN J21 [get_ports XcvSelect_pad_0_o]
+set_property PACKAGE_PIN A17 [get_ports XcvSelect_pad_1_o]
+set_property PACKAGE_PIN Y7 [get_ports or1200_clmode]
+set_property PACKAGE_PIN W10 [get_ports or1200_pic_ints]
+set_property PACKAGE_PIN AB12 [get_ports {or1200_pm_out[0]}]
+set_property PACKAGE_PIN AC12 [get_ports {or1200_pm_out[1]}]
+set_property PACKAGE_PIN AA10 [get_ports {or1200_pm_out[2]}]
+set_property PACKAGE_PIN AB10 [get_ports {or1200_pm_out[3]}]
+set_property PACKAGE_PIN G25 [get_ports phy_rst_pad_0_o]
+set_property PACKAGE_PIN F15 [get_ports phy_rst_pad_1_o]
+set_property PACKAGE_PIN W9 [get_ports reset]
+set_property PACKAGE_PIN  AB11 [get_ports {sysClk}]
+set_property PACKAGE_PIN H23 [get_ports usb_vbus_pad_0_i]
+set_property PACKAGE_PIN B19 [get_ports usb_vbus_pad_1_i]
+
+set_property LOC IBUFDS_GTE2_X0Y0 [get_cells mgtEngine/gt_usrclk_source/ibufds_instQ0_CLK1]
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells mgtEngine/gt_usrclk_source/ibufds_instQ0_CLK0]
+set_property LOC IBUFDS_GTE2_X0Y2 [get_cells mgtEngine/gt_usrclk_source/ibufds_instQ1_CLK1]
+set_property LOC IBUFDS_GTE2_X0Y3 [get_cells mgtEngine/gt_usrclk_source/ibufds_instQ1_CLK0]
+