diff options
Diffstat (limited to 'constraints-deel2/constraints-deel2.xpr')
| -rw-r--r-- | constraints-deel2/constraints-deel2.xpr | 75 |
1 files changed, 31 insertions, 44 deletions
diff --git a/constraints-deel2/constraints-deel2.xpr b/constraints-deel2/constraints-deel2.xpr index 4c8b342..6a2d165 100644 --- a/constraints-deel2/constraints-deel2.xpr +++ b/constraints-deel2/constraints-deel2.xpr @@ -1,9 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2022.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> -<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/constraints-deel2/constraints-deel2.xpr"> +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/constraints-deel2/constraints-deel2.xpr"> <DefaultLaunch Dir="$PRUNDIR"/> <Configuration> <Option Name="Id" Val="a5b3700692c54208a72337240cb41b13"/> @@ -28,14 +29,14 @@ <Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> - <Option Name="SimulatorVersionXsim" Val="2022.2"/> - <Option Name="SimulatorVersionModelSim" Val="2022.2"/> - <Option Name="SimulatorVersionQuesta" Val="2022.2"/> - <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> - <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> - <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> - <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> @@ -43,8 +44,7 @@ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> <Option Name="TargetLanguage" Val="VHDL"/> - <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> - <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="BoardPart" Val=""/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="ProjectType" Val="Default"/> @@ -60,6 +60,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> @@ -88,40 +89,40 @@ <Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> </Configuration> - <FileSets Version="1" Minor="31"> + <FileSets Version="1" Minor="32"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/fulladder1bit.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/fulladder1bit.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/fulladder2bit.vhd"> + <File Path="$PPRDIR/../copyright/prog2/fulladder2bit.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/gen_ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/gen_ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/gen_sync_ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/gen_sync_ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/adder16bit2bitfa.vhd"> + <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> @@ -131,29 +132,29 @@ <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="adder16bit2bitfa"/> <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="dataflowViewerSettings" Val="min_width=16"/> </Config> </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> <Filter Type="Constrs"/> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/adder16bit2bitfa.xdc"> + <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa.xdc"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/io.xdc"> + <File Path="$PPRDIR/../copyright/prog2/io.xdc"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> </FileInfo> </File> <Config> - <Option Name="TargetConstrsFile" Val="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/adder16bit2bitfa.xdc"/> + <Option Name="TargetConstrsFile" Val="$PPRDIR/../copyright/prog2/adder16bit2bitfa.xdc"/> <Option Name="ConstrsType" Val="XDC"/> </Config> </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="adder16bit2bitfa"/> @@ -171,14 +172,6 @@ </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> <Filter Type="Utils"/> - <File Path="$PSRCDIR/utils_1/imports/synth_1/adder16bit2bitfa.dcp"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - <Attr Name="UsedInSteps" Val="synth_1"/> - <Attr Name="AutoDcp" Val="1"/> - </FileInfo> - </File> <Config> <Option Name="TopAutoSet" Val="TRUE"/> </Config> @@ -205,12 +198,10 @@ <Option Name="Description" Val="Riviera-PRO Simulator"/> </Simulator> </Simulators> - <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/adder16bit2bitfa.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Runs Version="1" Minor="21"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"> <Option Id="FlattenHierarchy">0</Option> </Step> @@ -220,11 +211,9 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 1 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> @@ -241,9 +230,7 @@ <RQSFiles/> </Run> </Runs> - <Board> - <Jumpers/> - </Board> + <Board/> <DashboardSummary Version="1" Minor="0"> <Dashboards> <Dashboard Name="default_dashboard"> |