diff options
Diffstat (limited to 'adder-and-display')
4 files changed, 138 insertions, 22 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd new file mode 100644 index 0000000..2c8d6f5 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd @@ -0,0 +1,77 @@ +library IEEE; +library UNISIM; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +use UNISIM.VCOMPONENTS.ALL; + +entity dispdrv_tb is +end dispdrv_tb; + +architecture Behavioral of dispdrv_tb is +component dispdrv port ( + CLK: in std_logic; + D0: in std_logic_vector(7 downto 0); + D1: in std_logic_vector(7 downto 0); + D2: in std_logic_vector(7 downto 0); + D3: in std_logic_vector(7 downto 0); + D: out std_logic_vector(7 downto 0); + S: out std_logic_vector(1 downto 0)); +end component; +signal CLK: std_logic; +signal D0: std_logic_vector(7 downto 0); +signal D1: std_logic_vector(7 downto 0); +signal D2: std_logic_vector(7 downto 0); +signal D3: std_logic_vector(7 downto 0); +signal D: std_logic_vector(7 downto 0); +signal S: std_logic_vector(1 downto 0); + +signal test_case: std_logic_vector(1 downto 0); +signal OK: boolean := true; +begin + test: dispdrv port map( + CLK => CLK, + D0 => D0, + D1 => D1, + D2 => D2, + D3 => D3, + D => D, + S => S); + + tb: process + variable D0_t: std_logic_vector(7 downto 0) := b"00001111"; + variable D1_t: std_logic_vector(7 downto 0) := b"11110000"; + variable D2_t: std_logic_vector(7 downto 0) := b"01010101"; + variable D3_t: std_logic_vector(7 downto 0) := b"10101010"; + begin + + D0 <= D0_t; + D1 <= D1_t; + D2 <= D2_t; + D3 <= D3_t; + + for test_i in 0 to 3 loop + test_case <= std_logic_vector(to_unsigned(test_i, 2)); + CLK <= '0'; + wait for 5 ns; + CLK <= '1'; + wait for 5 ns; + + if test_case = 0 and D /= D0_t then + OK <= false; + end if; + if test_case = 1 and D /= D1_t then + OK <= false; + end if; + if test_case = 2 and D /= D2_t then + OK <= false; + end if; + if test_case = 3 and D /= D3_t then + OK <= false; + end if; + end loop; + wait; + end process; +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd new file mode 100644 index 0000000..548c9e5 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd @@ -0,0 +1,33 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity bin2bcd is port( + I: in std_logic_vector(4 downto 0); + X: out std_logic_vector(3 downto 0); + Y: out std_logic_vector(3 downto 0)); +end bin2bcd; + +architecture Behavioral of bin2bcd is +begin + with I select + X <= + b"0000" when b"00000" | b"01010" | b"10100" | b"11110", + b"0001" when b"00001" | b"01011" | b"10101" | b"11111", + b"0010" when b"00010" | b"01100" | b"10110", + b"0011" when b"00011" | b"01101" | b"10111", + b"0100" when b"00100" | b"01110" | b"11000", + b"0101" when b"00101" | b"01111" | b"11001", + b"0110" when b"00110" | b"10000" | b"11010", + b"0111" when b"00111" | b"10001" | b"11011", + b"1000" when b"01000" | b"10010" | b"11100", + b"1001" when b"01001" | b"10011" | b"11101", + (others => '0') when others; + with I select + Y <= + b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001", + b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011", + b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101", + b"0011" when b"11110" | b"11111", + (others => '0') when others; +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd index 6f6cb71..92e306e 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd @@ -38,7 +38,8 @@ architecture Behavioral of main is DS: out std_logic_vector(3 downto 0)); end component; signal X: std_logic_vector(3 downto 0); -- add out - signal Cout: std_logic; -- add carry out + signal Cout: std_logic; -- carry out + signal AOW: std_logic_vector(4 downto 0); -- add out wide (5-bit) signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0 signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1 signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock @@ -55,28 +56,20 @@ begin B => B, Cin => '0', X => X, - Cout => open); - -- bcd: component bin2bcd - -- port map ( - -- I => Cout & X, - -- X => BCD0, - -- Y => BCD1); - -- disp: component bcd2disp - -- port map ( - -- CLK => CLK_T(19), - -- N0 => BCD0, - -- N1 => BCD1, - -- N2 => "0000", - -- N3 => "0000", - -- DD => DD, - -- DS => DS); + Cout => Cout); + AOW <= Cout & X; + bcd: component bin2bcd + port map ( + I => AOW, + X => BCD0, + Y => BCD1); disp: component bcd2disp port map ( CLK => CLK_T(18), - N0 => X, - N1 => X, - N2 => "0000", - N3 => "0000", + N0 => "0000", + N1 => "0000", + N2 => BCD1, + N3 => BCD0, DD => DD, DS => DS); end Behavioral; diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr index 99e8c05..6b72430 100644 --- a/adder-and-display/adder-and-display.xpr +++ b/adder-and-display/adder-and-display.xpr @@ -60,7 +60,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="16"/> + <Option Name="WTXSimLaunchSim" Val="17"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -133,6 +133,12 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sources_1/bin2bcd.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="main"/> @@ -161,6 +167,12 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sim_1/dispdrv_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="bin2bcd_tb"/> @@ -223,7 +235,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -236,6 +248,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> |