3 files changed, 53 insertions, 18 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
new file mode 100644
index 0000000..4bb18bb
--- /dev/null
+++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bin2bcd is port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end bin2bcd;
+
+architecture Behavioral of bin2bcd is
+begin
+	with I select
+		X <=
+			x"0" when x"00" | x"0a" | x"14" | x"1e",
+			x"1" when x"01" | x"0b" | x"15" | x"1f",
+			x"2" when x"02" | x"0c" | x"16",
+			x"3" when x"03" | x"0d" | x"17",
+			x"4" when x"04" | x"0e" | x"18",
+			x"5" when x"05" | x"0f" | x"19",
+			x"6" when x"06" | x"10" | x"1a",
+			x"7" when x"07" | x"11" | x"1b",
+			x"8" when x"08" | x"12" | x"1c",
+			x"9" when x"09" | x"13" | x"1d",
+			(others => '0') when others;
+	with I select
+		Y <=
+			x"0" when x"00" | x"01" | x"02" | x"03" | x"04" | x"05" | x"06" | x"07" | x"08" | x"09",
+			x"1" when x"0a" | x"0b" | x"0c" | x"0d" | x"0e" | x"0f" | x"10" | x"11" | x"12" | x"13",
+			x"2" when x"14" | x"15" | x"16" | x"17" | x"18" | x"19" | x"1a" | x"1b" | x"1c" | x"1d",
+			x"3" when x"1e" | x"1f",
+			(others => '0') when others;
+end Behavioral;
+
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
index 907d8cc..92e306e 100644
--- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
@@ -23,7 +23,7 @@ architecture Behavioral of main is
 	end component;
 	component bin2bcd
 		port (
-			I: in std_logic_vector(3 downto 0);
+			I: in std_logic_vector(4 downto 0);
 			X: out std_logic_vector(3 downto 0);
 			Y: out std_logic_vector(3 downto 0));
 	end component;
@@ -38,6 +38,8 @@ architecture Behavioral of main is
 			DS: out std_logic_vector(3 downto 0));
 	end component;
 	signal X: std_logic_vector(3 downto 0); -- add out
+	signal Cout: std_logic; -- carry out
+	signal AOW: std_logic_vector(4 downto 0); -- add out wide (5-bit)
 	signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0
 	signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1
 	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
@@ -54,26 +56,20 @@ begin
 			B => B,
 			Cin => '0',
 			X => X,
-			Cout => open);
-	-- bcd: component bin2bcd
-	-- 	port map (
-	-- 		I => X,
-	-- 		X => BCD0,
-	-- 		Y => BCD1);
-	-- disp: component bcd2disp
-	-- 	port map (
-	-- 		CLK => CLK_T(19),
-	-- 		N0 => BCD0,
-	-- 		N1 => BCD1,
-	-- 		N2 => "0000",
-	-- 		N3 => "0000");
+			Cout => Cout);
+  AOW <= Cout & X;
+	bcd: component bin2bcd
+		port map (
+			I => AOW,
+			X => BCD0,
+			Y => BCD1);
 	disp: component bcd2disp
 		port map (
 			CLK => CLK_T(18),
-			N0 => X,
-			N1 => X,
-			N2 => "0000",
-			N3 => "0000",
+			N0 => "0000",
+			N1 => "0000",
+			N2 => BCD1,
+			N3 => BCD0,
 			DD => DD,
 			DS => DS);
 end Behavioral;
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr
index 2ff8357..5dcc304 100644
--- a/adder-and-display/adder-and-display.xpr
+++ b/adder-and-display/adder-and-display.xpr
@@ -114,6 +114,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/bin2bcd.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/dispdrv.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>