diff options
Diffstat (limited to 'adder-and-display/adder-and-display.srcs')
4 files changed, 161 insertions, 65 deletions
diff --git a/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc b/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc new file mode 100644 index 0000000..b90a3ca --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/constrs_1/main.xdc @@ -0,0 +1,51 @@ +set_property IOSTANDARD LVCMOS33 [get_ports CLK] +set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DD[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DS[0]}] +set_property PACKAGE_PIN W17 [get_ports {A[3]}] +set_property PACKAGE_PIN W16 [get_ports {A[2]}] +set_property PACKAGE_PIN V16 [get_ports {A[1]}] +set_property PACKAGE_PIN V17 [get_ports {A[0]}] +set_property PACKAGE_PIN W13 [get_ports {B[3]}] +set_property PACKAGE_PIN W14 [get_ports {B[2]}] +set_property PACKAGE_PIN V15 [get_ports {B[1]}] +set_property PACKAGE_PIN W15 [get_ports {B[0]}] +set_property PACKAGE_PIN W5 [get_ports CLK] +set_property PACKAGE_PIN V7 [get_ports {DD[7]}] +set_property PACKAGE_PIN U7 [get_ports {DD[6]}] +set_property PACKAGE_PIN V5 [get_ports {DD[5]}] +set_property PACKAGE_PIN U5 [get_ports {DD[4]}] +set_property PACKAGE_PIN V8 [get_ports {DD[3]}] +set_property PACKAGE_PIN U8 [get_ports {DD[2]}] +set_property PACKAGE_PIN W6 [get_ports {DD[1]}] +set_property PACKAGE_PIN W7 [get_ports {DD[0]}] +set_property PACKAGE_PIN U2 [get_ports {DS[3]}] +set_property PACKAGE_PIN U4 [get_ports {DS[2]}] +set_property PACKAGE_PIN V4 [get_ports {DS[1]}] +set_property PACKAGE_PIN W4 [get_ports {DS[0]}] + +set_property PULLDOWN true [get_ports {DD[7]}] +set_property PULLDOWN true [get_ports {DD[6]}] +set_property PULLDOWN true [get_ports {DD[5]}] +set_property PULLDOWN true [get_ports {DD[4]}] +set_property PULLDOWN true [get_ports {DD[3]}] +set_property PULLDOWN true [get_ports {DD[2]}] +set_property PULLDOWN true [get_ports {DD[1]}] +set_property PULLDOWN true [get_ports {DD[0]}] diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd index dd0fa11..f549ae5 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd @@ -6,8 +6,7 @@ entity bcd2disp is port( N0: in std_logic_vector(3 downto 0); N1: in std_logic_vector(3 downto 0); N2: in std_logic_vector(3 downto 0); - N3: in std_logic_vector(3 downto 0)); - + N3: in std_logic_vector(3 downto 0); DD: out std_logic_vector(7 downto 0); -- display segment data DS: out std_logic_vector(3 downto 0)); -- display select end bcd2disp; @@ -18,29 +17,54 @@ architecture Behavioral of bcd2disp is A: in std_logic_vector(3 downto 0); X: out std_logic_vector(7 downto 0)); end component; - signal D0: std_logic_vector(7 downto 0); -- display 0 segment bits - signal D1: std_logic_vector(7 downto 0); -- display 1 segment bits - signal D2: std_logic_vector(7 downto 0); -- display 2 segment bits - signal D3: std_logic_vector(7 downto 0); -- display 3 segment bits - + component dispdrv + port ( + CLK: in std_logic; + D0: in std_logic_vector(7 downto 0); + D1: in std_logic_vector(7 downto 0); + D2: in std_logic_vector(7 downto 0); + D3: in std_logic_vector(7 downto 0); + D: out std_logic_vector(7 downto 0); + S: out std_logic_vector(1 downto 0)); + end component; + signal D0: std_logic_vector(7 downto 0); -- display 0 segment bits + signal D1: std_logic_vector(7 downto 0); -- display 1 segment bits + signal D2: std_logic_vector(7 downto 0); -- display 2 segment bits + signal D3: std_logic_vector(7 downto 0); -- display 3 segment bits signal SX: std_logic_vector(1 downto 0); -- output display mux select - signal DX: std_logic_vector(7 downto 0); -- output display segment bits + signal DX: std_logic_vector(7 downto 0); -- output display segment data begin - bcddec0: component bcddec - port map ( - A => N0, - X => D0); - bcddec1: component bcddec - port map ( - A => N1, - X => D1); - bcddec2: component bcddec - port map ( - A => N2, - X => D2); - bcddec3: component bcddec - port map ( - A => N3, - X => D3); + bcddec0: component bcddec + port map ( + A => N0, + X => D0); + bcddec1: component bcddec + port map ( + A => N1, + X => D1); + bcddec2: component bcddec + port map ( + A => N2, + X => D2); + bcddec3: component bcddec + port map ( + A => N3, + X => D3); + + drv: component dispdrv + port map ( + CLK => CLK, + D0 => D0, + D1 => D1, + D2 => D2, + D3 => D3, + D => DX, + S => SX); + + DD <= not DX; + DS <= "1110" when SX = "00" else + "1101" when SX = "01" else + "1011" when SX = "10" else + "0111" when SX = "11"; end Behavioral; diff --git a/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd b/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd index 96b2c97..2a826ae 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd @@ -1,5 +1,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dispdrv is port ( diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd index af68d2b..907d8cc 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd @@ -1,5 +1,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; entity main is port( @@ -10,52 +12,69 @@ entity main is DS: out std_logic_vector(3 downto 0)); -- display select end main; -bcd2disp bcddec dispdrv architecture Behavioral of main is - component add4b - port ( - A: in std_logic_vector(3 downto 0); - B: in std_logic_vector(3 downto 0); - Cin: in std_logic; - X: out std_logic_vector(3 downto 0); - Cout: out std_logic); - end component; - component bin2bcd - port ( - I: in std_logic_vector(3 downto 0); - X: out std_logic_vector(3 downto 0); - Y: out std_logic_vector(3 downto 0); - end component; - component bcd2disp - port ( + component add4b + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + X: out std_logic_vector(3 downto 0); + Cout: out std_logic); + end component; + component bin2bcd + port ( + I: in std_logic_vector(3 downto 0); + X: out std_logic_vector(3 downto 0); + Y: out std_logic_vector(3 downto 0)); + end component; + component bcd2disp + port ( CLK: in std_logic; N0: in std_logic_vector(3 downto 0); N1: in std_logic_vector(3 downto 0); N2: in std_logic_vector(3 downto 0); - N3: in std_logic_vector(3 downto 0)); - end component; - signal X: std_logic_vector(4 downto 0); -- add out - signal BCD0: std_logic_vector(4 downto 0); -- bcd 10^0 - signal BCD1: std_logic_vector(4 downto 0); -- bcd 10^1 + N3: in std_logic_vector(3 downto 0); + DD: out std_logic_vector(7 downto 0); + DS: out std_logic_vector(3 downto 0)); + end component; + signal X: std_logic_vector(3 downto 0); -- add out + signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0 + signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1 + signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock begin - add: component add4b - port map ( - A => A, - B => B, - Cin => 0, - X => X, - Cout => 0); - bcd: component bin2bcd - port map ( - I => X, - X => BCD0, - Y => BCD1); - disp: component bcd2disp - port map ( - CLK => CLK, - N0 => BCD0, - N1 => BCD1, - N2 => 0, - N3 => 0); + process(CLK) + begin + if rising_edge(CLK) then + CLK_T <= (CLK_T + 1); + end if; + end process; + add: component add4b + port map ( + A => A, + B => B, + Cin => '0', + X => X, + Cout => open); + -- bcd: component bin2bcd + -- port map ( + -- I => X, + -- X => BCD0, + -- Y => BCD1); + -- disp: component bcd2disp + -- port map ( + -- CLK => CLK_T(19), + -- N0 => BCD0, + -- N1 => BCD1, + -- N2 => "0000", + -- N3 => "0000"); + disp: component bcd2disp + port map ( + CLK => CLK_T(18), + N0 => X, + N1 => X, + N2 => "0000", + N3 => "0000", + DD => DD, + DS => DS); end Behavioral; |