diff options
-rw-r--r-- | .gitignore | 4 | ||||
-rw-r--r-- | keyboard/keyboard.xpr | 6 | ||||
-rw-r--r-- | src/dispshift.vhd | 26 | ||||
-rw-r--r-- | src/scancodefilter.vhd | 64 |
4 files changed, 93 insertions, 7 deletions
@@ -18,3 +18,7 @@ copyright/ # drawio **/.$* + +# vivado troep +*.log +*.jou diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr index c04a26b..270bd7f 100644 --- a/keyboard/keyboard.xpr +++ b/keyboard/keyboard.xpr @@ -197,16 +197,17 @@ </Simulator> </Simulators> <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -219,6 +220,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> diff --git a/src/dispshift.vhd b/src/dispshift.vhd index 5669641..4c4093b 100644 --- a/src/dispshift.vhd +++ b/src/dispshift.vhd @@ -11,7 +11,29 @@ end dispshift; architecture Behavioral of dispshift is -begin - +-- init as empty display +signal sD: std_logic_vector(11 downto 0) := x"aaa"; +signal SLastValue: std_logic := '0'; +begin + process(CLK) + begin + if (rising_edge (clk)) then + -- set default values + SLastValue <= S; + sD <= sD; + + -- when S does go high update output + if (SLastValue = '0' and S = '1') then + -- set data on output + N3 <= sD(11 downto 8); + N2 <= sD(7 downto 4); + N1 <= sD(3 downto 0); + N0 <= D; + + -- store new data + sD <= sD(7 downto 0) & D; + end if; + end if; + end process; end Behavioral; diff --git a/src/scancodefilter.vhd b/src/scancodefilter.vhd index 518c3aa..dbdf7b7 100644 --- a/src/scancodefilter.vhd +++ b/src/scancodefilter.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; ---use ieee.numeric_std.all; +use ieee.numeric_std.all; entity scancodefilter is port( CLK: in std_logic; -- system clock @@ -12,7 +12,65 @@ end scancodefilter; architecture Behavioral of scancodefilter is -begin - +-- init as empty key +--signal lastKey: std_logic_vector(3 downto 0) := x"a"; +signal lastNEW_DAT: std_logic := '0'; +signal DAT_OLD: std_logic_vector(7 downto 0); -- scancode preveouse input +begin + process(CLK) + begin + if (rising_edge (clk)) then + -- always set data on output + BCD <= x"a"; + SHIFT <= '0'; + lastNEW_DAT <= NEW_DAT; + DAT_OLD <= DAT_OLD; + + -- when NEW_DAT does go high + if ((lastNEW_DAT = '0') and (NEW_DAT = '1')) then + -- set DAT_OLD + DAT_OLD <= DAT; + + -- only is pervioause data is not release of key scancode and currend data + if (DAT_OLD /= x"F0" and DAT /= x"F0") then + case DAT is + when x"45" => + BCD <= std_logic_vector(to_unsigned(0, BCD'length)); + SHIFT <= '1'; + when x"16" => + BCD <= std_logic_vector(to_unsigned(1, BCD'length)); + SHIFT <= '1'; + when x"1E" => + BCD <= std_logic_vector(to_unsigned(2, BCD'length)); + SHIFT <= '1'; + when x"26" => + BCD <= std_logic_vector(to_unsigned(3, BCD'length)); + SHIFT <= '1'; + when x"25" => + BCD <= std_logic_vector(to_unsigned(4, BCD'length)); + SHIFT <= '1'; + when x"2E" => + BCD <= std_logic_vector(to_unsigned(5, BCD'length)); + SHIFT <= '1'; + when x"36" => + BCD <= std_logic_vector(to_unsigned(6, BCD'length)); + SHIFT <= '1'; + when x"3D" => + BCD <= std_logic_vector(to_unsigned(7, BCD'length)); + SHIFT <= '1'; + when x"3E" => + BCD <= std_logic_vector(to_unsigned(8, BCD'length)); + SHIFT <= '1'; + when x"46" => + BCD <= std_logic_vector(to_unsigned(9, BCD'length)); + SHIFT <= '1'; + when others => + BCD <= x"b"; + SHIFT <= '1'; + end case; + end if; + end if; + end if; + end process; end Behavioral; |