diff options
| l--------- | alu/alu.srcs/sim_1/bin2bcd8_tb.vhd | 1 | ||||
| l--------- | alu/alu.srcs/sources_1/bin2bcd8.vhd | 1 | ||||
| l--------- | alu/alu.srcs/sources_1/main.vhd | 1 | ||||
| -rw-r--r-- | alu/alu.xpr | 16 | ||||
| -rw-r--r-- | design/stopp.dig | 111 | ||||
| -rw-r--r-- | src/bin2bcd8.vhd | 17 | ||||
| -rw-r--r-- | src/bin2bcd8_tb.vhd | 48 | ||||
| -rw-r--r-- | src/main-alu.vhd | 0 |
8 files changed, 190 insertions, 5 deletions
diff --git a/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd b/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd new file mode 120000 index 0000000..77c87bd --- /dev/null +++ b/alu/alu.srcs/sim_1/bin2bcd8_tb.vhd @@ -0,0 +1 @@ +../../../src/bin2bcd8_tb.vhd
\ No newline at end of file diff --git a/alu/alu.srcs/sources_1/bin2bcd8.vhd b/alu/alu.srcs/sources_1/bin2bcd8.vhd new file mode 120000 index 0000000..e5ecc75 --- /dev/null +++ b/alu/alu.srcs/sources_1/bin2bcd8.vhd @@ -0,0 +1 @@ +../../../src/bin2bcd8.vhd
\ No newline at end of file diff --git a/alu/alu.srcs/sources_1/main.vhd b/alu/alu.srcs/sources_1/main.vhd new file mode 120000 index 0000000..332f933 --- /dev/null +++ b/alu/alu.srcs/sources_1/main.vhd @@ -0,0 +1 @@ +../../../src/main-alu.vhd
\ No newline at end of file diff --git a/alu/alu.xpr b/alu/alu.xpr index bb1f73a..4b0551d 100644 --- a/alu/alu.xpr +++ b/alu/alu.xpr @@ -59,7 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="39"/> + <Option Name="WTXSimLaunchSim" Val="41"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -162,19 +162,19 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PSRCDIR/sources_1/binary_to_bcd_digit.vhd"> + <File Path="$PSRCDIR/sources_1/add8bs.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PSRCDIR/sources_1/binary_to_bcd.vhd"> + <File Path="$PSRCDIR/sources_1/main.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PSRCDIR/sources_1/add8bs.vhd"> + <File Path="$PSRCDIR/sources_1/bin2bcd8.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> @@ -207,9 +207,15 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sim_1/bin2bcd8_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="ALU_TB"/> + <Option Name="TopModule" Val="bin2bcd8_tb"/> <Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/> diff --git a/design/stopp.dig b/design/stopp.dig new file mode 100644 index 0000000..3a8750e --- /dev/null +++ b/design/stopp.dig @@ -0,0 +1,111 @@ +<?xml version="1.0" encoding="utf-8"?> +<circuit> + <version>1</version> + <attributes/> + <visualElements> + <visualElement> + <elementName>2c.dig</elementName> + <elementAttributes/> + <pos x="440" y="240"/> + </visualElement> + <visualElement> + <elementName>Multiplexer</elementName> + <elementAttributes> + <entry> + <string>Bits</string> + <int>8</int> + </entry> + </elementAttributes> + <pos x="540" y="200"/> + </visualElement> + <visualElement> + <elementName>Splitter</elementName> + <elementAttributes> + <entry> + <string>Input Splitting</string> + <string>8</string> + </entry> + <entry> + <string>Output Splitting</string> + <string>0-7,7-7</string> + </entry> + </elementAttributes> + <pos x="380" y="240"/> + </visualElement> + <visualElement> + <elementName>Out</elementName> + <elementAttributes> + <entry> + <string>Label</string> + <string>X</string> + </entry> + <entry> + <string>Bits</string> + <int>8</int> + </entry> + </elementAttributes> + <pos x="600" y="220"/> + </visualElement> + <visualElement> + <elementName>In</elementName> + <elementAttributes> + <entry> + <string>Label</string> + <string>A</string> + </entry> + <entry> + <string>Bits</string> + <int>8</int> + </entry> + </elementAttributes> + <pos x="340" y="240"/> + </visualElement> + </visualElements> + <wires> + <wire> + <p1 x="400" y="240"/> + <p2 x="420" y="240"/> + </wire> + <wire> + <p1 x="500" y="240"/> + <p2 x="540" y="240"/> + </wire> + <wire> + <p1 x="340" y="240"/> + <p2 x="380" y="240"/> + </wire> + <wire> + <p1 x="420" y="240"/> + <p2 x="440" y="240"/> + </wire> + <wire> + <p1 x="400" y="260"/> + <p2 x="420" y="260"/> + </wire> + <wire> + <p1 x="420" y="200"/> + <p2 x="540" y="200"/> + </wire> + <wire> + <p1 x="420" y="300"/> + <p2 x="560" y="300"/> + </wire> + <wire> + <p1 x="580" y="220"/> + <p2 x="600" y="220"/> + </wire> + <wire> + <p1 x="560" y="240"/> + <p2 x="560" y="300"/> + </wire> + <wire> + <p1 x="420" y="200"/> + <p2 x="420" y="240"/> + </wire> + <wire> + <p1 x="420" y="260"/> + <p2 x="420" y="300"/> + </wire> + </wires> + <measurementOrdering/> +</circuit>
\ No newline at end of file diff --git a/src/bin2bcd8.vhd b/src/bin2bcd8.vhd new file mode 100644 index 0000000..eb8c71d --- /dev/null +++ b/src/bin2bcd8.vhd @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; +-- use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity bin2bcd8 is port( + A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit) + X: out std_logic_vector(3 downto 0); -- bcd output + R: out std_logic_vector(7 downto 0)); -- remainder after operation +end bin2bcd8; + +architecture Behavioral of bin2bcd8 is +begin + X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4)); + R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, 8)); +end Behavioral; diff --git a/src/bin2bcd8_tb.vhd b/src/bin2bcd8_tb.vhd new file mode 100644 index 0000000..4e24471 --- /dev/null +++ b/src/bin2bcd8_tb.vhd @@ -0,0 +1,48 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; + +entity bin2bcd8_tb is +end bin2bcd8_tb; + +architecture Behavioral of bin2bcd8_tb is +component bin2bcd8 port( + A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit) + X: out std_logic_vector(3 downto 0); -- bcd output + R: out std_logic_vector(7 downto 0)); -- remainder after operation +end component; +-- test input +signal I: std_logic_vector(7 downto 0) := (others => '0'); +-- test output +signal X: std_logic_vector(3 downto 0); +signal R: std_logic_vector(7 downto 0); + +signal test_case: std_logic_vector(7 downto 0); +signal OK: boolean := true; +begin + test: bin2bcd8 port map( + A => I, + X => X, + R => R); + + tb: process + -- expected output + variable X_t: integer := 0; + variable Y_t: integer := 0; + begin + + for test_i in 0 to 255 loop + test_case <= std_logic_vector(to_unsigned(test_i,8)); + wait for 1 ps; + + I <= test_case; + + wait for 10 ns; + end loop; + wait; -- stop simulator + end process; +end Behavioral; + diff --git a/src/main-alu.vhd b/src/main-alu.vhd new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/main-alu.vhd |