diff options
| -rw-r--r-- | adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd | 22 | ||||
| -rw-r--r-- | adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd | 22 | ||||
| -rw-r--r-- | adder-and-display/adder-and-display.srcs/sources_1/main.vhd | 36 | ||||
| -rw-r--r-- | adder-and-display/adder-and-display.xpr | 240 | ||||
| -rw-r--r-- | blink/blink.srcs/sources_1/main.vhd | 4 |
5 files changed, 323 insertions, 1 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd new file mode 100644 index 0000000..7322509 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity bcddec is port( + A: in std_logic_vector(3 downto 0); + X: out std_logic_vector(6 downto 0)); +end bcddec; + +architecture Behavioral of bcddec is +begin + X <= "0111111" when A = "0000" else + "0000110" when A = "0001" else + "1011011" when A = "0010" else + "1001111" when A = "0011" else + "1100110" when A = "0100" else + "1101101" when A = "0101" else + "1111101" when A = "0110" else + "0100111" when A = "0111" else + "1111111" when A = "1000" else + "1101111" when A = "1001"; +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd new file mode 100644 index 0000000..fa6fdea --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2bcd is + port ( + A: in std_logic_vector(4 downto 0); + X: out std_logic_vector(3 downto 0); + Y: out std_logic_vector(3 downto 0)); +end bin2bcd; + +architecture Behavioral of bin2bcd is + signal X_tmp: unsigned(3 downto 0); + signal Y_tmp: unsigned(3 downto 0); +begin + X_tmp <= (unsigned(A(X_tmp'range)) / 10); + Y_tmp <= (unsigned(A(Y_tmp'range)) mod 10); + + X <= std_logic_vector(X_tmp); + Y <= std_logic_vector(Y_tmp); +end Behavioral; diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd new file mode 100644 index 0000000..448d0a7 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity main is + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + D1: out std_logic_vector(6 downto 0); + D2: out std_logic_vector(6 downto 0); + Cout: out std_logic); +end main; + +architecture Behavioral of main is +signal RESULT: std_logic_vector(3 downto 0); +signal BCD1: std_logic_vector(3 downto 0); +signal BCD2: std_logic_vector(3 downto 0); +begin + add: entity work.add4b port map ( + A => A, + B => B, + Cin => Cin, + X => RESULT, + Cout => Cout); + bcdconv: entity work.bin2bcd port map ( + A => RESULT, + X => BCD1, + Y => BCD2); + bcddec1: entity work.bcddec port map ( + A => BCD1, + X => D1); + bcddec2: entity work.bcddec port map ( + A => BCD2, + X => D2); +end Behavioral; + diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr new file mode 100644 index 0000000..4b2a52a --- /dev/null +++ b/adder-and-display/adder-and-display.xpr @@ -0,0 +1,240 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2022.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> + +<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/adder-and-display/adder-and-display.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="46be447dad084e2ab037b940624211d0"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2022.2"/> + <Option Name="SimulatorVersionModelSim" Val="2022.2"/> + <Option Name="SimulatorVersionQuesta" Val="2022.2"/> + <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> + <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> + <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> + <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> + <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="basys3"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="31"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PPRDIR/../full-adder/full-adder.srcs/sources_1/add4b.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/bcddec.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/bin2bcd.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/main.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="main"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="dataflowViewerSettings" Val="min_width=16"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="main"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="19"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board> + <Jumpers/> + </Board> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> diff --git a/blink/blink.srcs/sources_1/main.vhd b/blink/blink.srcs/sources_1/main.vhd index 12aff02..b6d1500 100644 --- a/blink/blink.srcs/sources_1/main.vhd +++ b/blink/blink.srcs/sources_1/main.vhd @@ -9,7 +9,9 @@ entity main is led : out STD_LOGIC); end main; -architecture Behavioral of main is signal count: STD_LOGIC_VECTOR(24 downto 0); +architecture Behavioral of main is signal + +count: STD_LOGIC_VECTOR(24 downto 0); begin process(clk) begin |