diff options
| -rw-r--r-- | full-adder/full-adder.srcs/sim_1/add4b_tb.vhd | 104 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sources_1/add4b.vhd | 99 | ||||
| -rw-r--r-- | full-adder/full-adder.xpr | 241 |
3 files changed, 444 insertions, 0 deletions
diff --git a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd new file mode 100644 index 0000000..2999486 --- /dev/null +++ b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd @@ -0,0 +1,104 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY UNISIM; +USE UNISIM.Vcomponents.ALL; +ENTITY add4b_tb IS +END add4b_tb; +ARCHITECTURE behavioral OF add4b_tb IS + COMPONENT add4b + Port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + X: out std_logic_vector(3 downto 0); + Cout: out std_logic); + END COMPONENT; + + SIGNAL A: std_logic_vector(3 downto 0); + SIGNAL B: std_logic_vector(3 downto 0); + SIGNAL S: std_logic_vector(3 downto 0); + SIGNAL C_out : STD_LOGIC; + SIGNAL C_in : STD_LOGIC; + Signal Test_case: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0'); + signal OK: boolean := true; + +BEGIN + UUT: add4b PORT MAP( + A => A, + B => B, + X => S, + Cout => C_out, + Cin => C_in); + +-- *** Test Bench - User Defined Section *** + tb : PROCESS + variable S0_t : STD_LOGIC; + variable S1_t : STD_LOGIC; + variable S2_t : STD_LOGIC; + variable S3_t : STD_LOGIC; + variable C_out_t : STD_LOGIC; + variable A_t : integer; + variable B_t : integer; + variable sum : integer; + + + BEGIN + C_in <= '0'; -- C_in is ignored in this test + for I in 0 to 255 loop + + Test_case <= Std_logic_vector(to_unsigned(I,8)); + A(0) <= Test_case(0); + A(1) <= Test_case(1); + A(2) <= Test_case(2); + A(3) <= Test_case(3); + B(0) <= Test_case(4); + B(1) <= Test_case(5); + B(2) <= Test_case(6); + B(3) <= Test_case(7); + + + A_t := To_integer(unsigned(test_case(3 downto 0))); + B_t := To_integer(unsigned(test_case(7 downto 4))); + sum := A_t+B_t; + + S0_t := to_unsigned(sum,5)(0); + S1_t := to_unsigned(sum,5)(1); + S2_t := to_unsigned(sum,5)(2); + S3_t := to_unsigned(sum,5)(3); + C_out_t := to_unsigned(sum,5)(4); + + wait for 5 ns; + + If S(0) /= S0_t then + OK <= false; + end if; + + if S(1) /= S1_t then + OK <= false; + end if; + + if S(2) /= S2_t then + OK <= false; + end if; + + if S(3) /= S3_t then + OK <= false; + end if; + + if C_out /= C_out_t then + OK <= false; + end if; + + wait for 5 ns; + + + end loop; + + + + WAIT; -- will wait forever + END PROCESS; +-- *** End Test Bench - User Defined Section *** + +END;
\ No newline at end of file diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd new file mode 100644 index 0000000..28c2c24 --- /dev/null +++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd @@ -0,0 +1,99 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity half_add is + port ( + A: in std_logic; + B: in std_logic; + X: out std_logic; + Cout: out std_logic); +end half_add; + +architecture Behavioral of half_add is +begin + Cout <= (A AND B); + X <= (A XOR B); +end Behavioral; + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity add1b is + port ( + A: in std_logic; + B: in std_logic; + Cin: in std_logic; + X: out std_logic; + Cout: out std_logic); +end add1b; + +architecture Behavioral of add1b is + signal s0: std_logic; + signal s1: std_logic; + signal s2: std_logic; +begin + add0: entity work.half_add + port map ( + A => A, + B => B, + X => s0, + Cout => s1); + add1: entity work.half_add + port map ( + A => Cin, + B => s0, + X => X, + Cout => s2); + Cout <= (s2 OR s1); +end Behavioral; + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity add4b is + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + X: out std_logic_vector(3 downto 0); + Cout: out std_logic); +end add4b; + +architecture Behavioral of add4b is + signal C0: std_logic; + signal C1: std_logic; + signal C2: std_logic; +begin + add0: entity work.add1b + port map ( + A => A(0), + B => B(0), + Cin => Cin, + X => X(0), + Cout => C0); + add1: entity work.add1b + port map ( + A => A(1), + B => B(1), + Cin => C0, + X => X(1), + Cout => C1); + add2: entity work.add1b + port map ( + A => A(2), + B => B(2), + Cin => C1, + X => X(2), + Cout => C2); + add3: entity work.add1b + port map ( + A => A(3), + B => B(3), + Cin => C2, + X => X(3), + Cout => Cout); +end Behavioral; + diff --git a/full-adder/full-adder.xpr b/full-adder/full-adder.xpr new file mode 100644 index 0000000..3063455 --- /dev/null +++ b/full-adder/full-adder.xpr @@ -0,0 +1,241 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2022.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> + +<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/full-adder/full-adder.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="49e7f3530433473f973bdccc4f13fdcc"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2022.2"/> + <Option Name="SimulatorVersionModelSim" Val="2022.2"/> + <Option Name="SimulatorVersionQuesta" Val="2022.2"/> + <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> + <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> + <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> + <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> + <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="basys3"/> + <Option Name="WTXSimLaunchSim" Val="1"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="31"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/add4b.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sim_1/add4b_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="add4b_tb"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="dataflowViewerSettings" Val="min_width=16"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <File Path="$PSRCDIR/sim_1/add4b_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="add4b_tb"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopArchitecture" Val="behavioral"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/add4b.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="19"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/add4b.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board> + <Jumpers/> + </Board> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> |