diff options
| -rw-r--r-- | blink/blink.srcs/constrs_1/consts.xdc (renamed from blink/blink.srcs/constrs_1/new/consts.xdc) | 0 | ||||
| -rw-r--r-- | blink/blink.srcs/sources_1/main.vhd (renamed from blink/blink.srcs/sources_1/new/main.vhd) | 0 | ||||
| -rw-r--r-- | blink/blink.xpr | 9 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sim_1/add4b_tb.vhd | 110 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sources_1/add4b.vhd | 17 | ||||
| -rw-r--r-- | full-adder/full-adder.xpr | 11 |
6 files changed, 70 insertions, 77 deletions
diff --git a/blink/blink.srcs/constrs_1/new/consts.xdc b/blink/blink.srcs/constrs_1/consts.xdc index 1b42b1d..1b42b1d 100644 --- a/blink/blink.srcs/constrs_1/new/consts.xdc +++ b/blink/blink.srcs/constrs_1/consts.xdc diff --git a/blink/blink.srcs/sources_1/new/main.vhd b/blink/blink.srcs/sources_1/main.vhd index 12aff02..12aff02 100644 --- a/blink/blink.srcs/sources_1/new/main.vhd +++ b/blink/blink.srcs/sources_1/main.vhd diff --git a/blink/blink.xpr b/blink/blink.xpr index 1621ba4..b10fa67 100644 --- a/blink/blink.xpr +++ b/blink/blink.xpr @@ -91,7 +91,7 @@ <FileSets Version="1" Minor="31"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> - <File Path="$PSRCDIR/sources_1/new/main.vhd"> + <File Path="$PSRCDIR/sources_1/main.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> @@ -106,14 +106,14 @@ </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> <Filter Type="Constrs"/> - <File Path="$PSRCDIR/constrs_1/new/consts.xdc"> + <File Path="$PSRCDIR/constrs_1/consts.xdc"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> </FileInfo> </File> <Config> - <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/consts.xdc"/> + <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/consts.xdc"/> <Option Name="ConstrsType" Val="XDC"/> </Config> </FileSet> @@ -181,7 +181,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -194,7 +194,6 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> - <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> diff --git a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd index 2999486..312cf22 100644 --- a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd +++ b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd @@ -1,52 +1,52 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY UNISIM; -USE UNISIM.Vcomponents.ALL; -ENTITY add4b_tb IS -END add4b_tb; -ARCHITECTURE behavioral OF add4b_tb IS - COMPONENT add4b - Port ( - A: in std_logic_vector(3 downto 0); - B: in std_logic_vector(3 downto 0); - Cin: in std_logic; - X: out std_logic_vector(3 downto 0); - Cout: out std_logic); - END COMPONENT; +library ieee; +library unisim; - SIGNAL A: std_logic_vector(3 downto 0); - SIGNAL B: std_logic_vector(3 downto 0); - SIGNAL S: std_logic_vector(3 downto 0); - SIGNAL C_out : STD_LOGIC; - SIGNAL C_in : STD_LOGIC; - Signal Test_case: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0'); - signal OK: boolean := true; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; -BEGIN - UUT: add4b PORT MAP( - A => A, - B => B, - X => S, - Cout => C_out, - Cin => C_in); +entity add4b_tb is +end add4b_tb; --- *** Test Bench - User Defined Section *** - tb : PROCESS - variable S0_t : STD_LOGIC; - variable S1_t : STD_LOGIC; - variable S2_t : STD_LOGIC; - variable S3_t : STD_LOGIC; - variable C_out_t : STD_LOGIC; - variable A_t : integer; - variable B_t : integer; - variable sum : integer; +architecture behavioral of add4b_tb is component add4b + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + X: out std_logic_vector(3 downto 0); + Cout: out std_logic); +end component; +signal A: std_logic_vector(3 downto 0); +signal B: std_logic_vector(3 downto 0); +signal S: std_logic_vector(3 downto 0); +signal C_out : STD_LOGIC; +signal C_in : STD_LOGIC; +signal Test_case: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0'); +signal OK: boolean := true; - BEGIN +begin + UUT: add4b port map( + A => A, + B => B, + X => S, + Cout => C_out, + Cin => C_in); + + tb: process + variable S0_t : STD_LOGIC; + variable S1_t : STD_LOGIC; + variable S2_t : STD_LOGIC; + variable S3_t : STD_LOGIC; + variable C_out_t : STD_LOGIC; + variable A_t : integer; + variable B_t : integer; + variable sum : integer; + + begin C_in <= '0'; -- C_in is ignored in this test for I in 0 to 255 loop - + Test_case <= Std_logic_vector(to_unsigned(I,8)); A(0) <= Test_case(0); A(1) <= Test_case(1); @@ -56,49 +56,35 @@ BEGIN B(1) <= Test_case(5); B(2) <= Test_case(6); B(3) <= Test_case(7); - - + A_t := To_integer(unsigned(test_case(3 downto 0))); B_t := To_integer(unsigned(test_case(7 downto 4))); sum := A_t+B_t; - + S0_t := to_unsigned(sum,5)(0); S1_t := to_unsigned(sum,5)(1); S2_t := to_unsigned(sum,5)(2); S3_t := to_unsigned(sum,5)(3); C_out_t := to_unsigned(sum,5)(4); - + wait for 5 ns; - If S(0) /= S0_t then OK <= false; end if; - if S(1) /= S1_t then OK <= false; end if; - if S(2) /= S2_t then OK <= false; end if; - if S(3) /= S3_t then OK <= false; end if; - if C_out /= C_out_t then OK <= false; end if; - wait for 5 ns; - - end loop; - - - - WAIT; -- will wait forever - END PROCESS; --- *** End Test Bench - User Defined Section *** - -END;
\ No newline at end of file + wait; -- stop for simulator + end process; +end; diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd index 28c2c24..e70862b 100644 --- a/full-adder/full-adder.srcs/sources_1/add4b.vhd +++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd @@ -2,6 +2,7 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; +-- half adder entity entity half_add is port ( A: in std_logic; @@ -16,10 +17,13 @@ begin X <= (A XOR B); end Behavioral; + + LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; +-- full adder entity entity add1b is port ( A: in std_logic; @@ -34,25 +38,31 @@ architecture Behavioral of add1b is signal s1: std_logic; signal s2: std_logic; begin + -- first add A and B with HA add0: entity work.half_add port map ( A => A, B => B, X => s0, Cout => s1); + -- then add first result with Cin to get final result add1: entity work.half_add port map ( A => Cin, B => s0, X => X, Cout => s2); + -- calculate Cout by OR-ing the Cout of both half adders Cout <= (s2 OR s1); end Behavioral; + + LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; +-- full 4-bit adder entity entity add4b is port ( A: in std_logic_vector(3 downto 0); @@ -63,10 +73,11 @@ entity add4b is end add4b; architecture Behavioral of add4b is - signal C0: std_logic; - signal C1: std_logic; - signal C2: std_logic; + signal C0: std_logic; -- Cout0 -> Cin1 + signal C1: std_logic; -- Cout1 -> Cin2 + signal C2: std_logic; -- Cout2 -> Cin3 begin + -- full adder ladder (e.g. Cin -> Cin0, Cout0 -> Cin1, ..., Cout3 -> Cout) add0: entity work.add1b port map ( A => A(0), diff --git a/full-adder/full-adder.xpr b/full-adder/full-adder.xpr index 3063455..4fcc50a 100644 --- a/full-adder/full-adder.xpr +++ b/full-adder/full-adder.xpr @@ -59,7 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="1"/> + <Option Name="WTXSimLaunchSim" Val="2"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -116,6 +116,7 @@ </Config> </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> <File Path="$PSRCDIR/sim_1/add4b_tb.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> @@ -177,9 +178,7 @@ <Runs Version="1" Minor="19"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/add4b.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> @@ -188,9 +187,7 @@ </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> |