diff options
| author | lonkaars <loek@pipeframe.xyz> | 2022-12-20 15:28:32 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2022-12-20 15:28:32 +0100 |
| commit | 3ef260fca9f941d7c56cf8ca1978fe91ff61b2a1 (patch) | |
| tree | 430a20fd402f56e9aa2929a08390fc7d50237f83 /src | |
| parent | d383e3742a4d38a3eb5899d9891cd06ba044dcac (diff) | |
fix vga phase by using sysclk in pixeldata module
Diffstat (limited to 'src')
| -rw-r--r-- | src/main-bouncing-ball.vhd | 3 | ||||
| -rw-r--r-- | src/pixeldata-ball.vhd | 16 |
2 files changed, 5 insertions, 14 deletions
diff --git a/src/main-bouncing-ball.vhd b/src/main-bouncing-ball.vhd index 83b60f7..0a59ca6 100644 --- a/src/main-bouncing-ball.vhd +++ b/src/main-bouncing-ball.vhd @@ -19,7 +19,7 @@ architecture Behavioral of main is hsync, vsync: out std_logic); end component; component pixeldata port ( - sys_clk, pixel_clk, bounce_clk, reset: in std_logic; + sys_clk, bounce_clk, reset: in std_logic; x, y: in std_logic_vector(9 downto 0); rgb: out std_logic_vector(11 downto 0)); end component; @@ -41,7 +41,6 @@ begin pixel: component pixeldata port map ( sys_clk => clk, - pixel_clk => clk25(1), bounce_clk => vsync_inv, reset => reset, x => x, diff --git a/src/pixeldata-ball.vhd b/src/pixeldata-ball.vhd index 7d72cce..f4fab56 100644 --- a/src/pixeldata-ball.vhd +++ b/src/pixeldata-ball.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; entity pixeldata is port ( - sys_clk, pixel_clk, bounce_clk, reset: in std_logic; + sys_clk, bounce_clk, reset: in std_logic; x, y: in std_logic_vector(9 downto 0); rgb: out std_logic_vector(11 downto 0)); end pixeldata; @@ -37,20 +37,12 @@ begin clka => sys_clk, addra => bitmap_idx, douta => bitmap_out); - process(pixel_clk) + process(sys_clk) begin - if rising_edge(pixel_clk) then - -- send bitmap address to rom chip early - if (x >= 639) and (sx = 0) and (y >= sy) and (y < (sy + 10)) then - -- exception for first display column - bitmap_idx <= std_logic_vector(resize(unsigned(y - sy + 1) * 10, bitmap_idx'length)); - elsif ((x + 1) >= sx) and ((x + 1) < (sx + 10)) and (y >= sy) and (y < (sy + 10)) then - -- regular early (horizontal shift) - bitmap_idx <= std_logic_vector(resize(unsigned(x + 1 - sx) + unsigned(y - sy) * 10, bitmap_idx'length)); - end if; - + if rising_edge(sys_clk) then if (x >= sx) and (x < (sx + 10)) and (y >= sy) and (y < (sy + 10)) then -- draw ball + bitmap_idx <= std_logic_vector(resize(unsigned(x - sx) + unsigned(y - sy) * 10, bitmap_idx'length)); rgb <= bitmap_out; else -- blue background |