add 1-bit full adder test bench and seperate files

3 files changed, 61 insertions, 67 deletions

diff --git a/full-adder/full-adder.srcs/sources_1/add1b.vhd b/full-adder/full-adder.srcs/sources_1/add1b.vhd
new file mode 100644
index 0000000..a2d4068
--- /dev/null
+++ b/full-adder/full-adder.srcs/sources_1/add1b.vhd
@@ -0,0 +1,43 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- full adder entity
+entity add1b is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    Cin: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end add1b;
+
+architecture Behavioral of add1b is
+  signal s0: std_logic;
+  signal s1: std_logic;
+  signal s2: std_logic;
+  component half_add
+	port (
+	  A: in std_logic;
+      B: in std_logic;
+      X: out std_logic;
+      Cout: out std_logic);
+  end component;
+begin
+	-- first add A and B with HA
+	add0: component half_add
+    port map (
+      A => A,
+      B => B,
+      X => s0,
+      Cout => s1);
+	-- then add first result with Cin to get final result
+  add1: component half_add
+    port map (
+      A => Cin,
+      B => s0,
+      X => X,
+      Cout => s2);
+	-- calculate Cout by OR-ing the Cout of both half adders
+  Cout <= (s2 OR s1);
+end Behavioral;
diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd
index 184d360..07e5a22 100644
--- a/full-adder/full-adder.srcs/sources_1/add4b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd
@@ -2,73 +2,6 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
 
--- half adder entity
-entity half_add is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end half_add;
-
-architecture Behavioral of half_add is
-begin
-  Cout <= (A AND B);
-  X <= (A XOR B);
-end Behavioral;
-
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full adder entity
-entity add1b is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    Cin: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end add1b;
-
-architecture Behavioral of add1b is
-  signal s0: std_logic;
-  signal s1: std_logic;
-  signal s2: std_logic;
-  component half_add
-	port (
-	  A: in std_logic;
-      B: in std_logic;
-      X: out std_logic;
-      Cout: out std_logic);
-  end component;
-begin
-	-- first add A and B with HA
-	add0: component half_add
-    port map (
-      A => A,
-      B => B,
-      X => s0,
-      Cout => s1);
-	-- then add first result with Cin to get final result
-  add1: component half_add
-    port map (
-      A => Cin,
-      B => s0,
-      X => X,
-      Cout => s2);
-	-- calculate Cout by OR-ing the Cout of both half adders
-  Cout <= (s2 OR s1);
-end Behavioral;
-
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
 -- full 4-bit adder entity
 entity add4b is
   port (
diff --git a/full-adder/full-adder.srcs/sources_1/half_add.vhd b/full-adder/full-adder.srcs/sources_1/half_add.vhd
new file mode 100644
index 0000000..d2d340a
--- /dev/null
+++ b/full-adder/full-adder.srcs/sources_1/half_add.vhd
@@ -0,0 +1,18 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- half adder entity
+entity half_add is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end half_add;
+
+architecture Behavioral of half_add is
+begin
+  Cout <= (A AND B);
+  X <= (A XOR B);
+end Behavioral;