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| author | lonkaars <loek@pipeframe.xyz> | 2022-11-11 11:51:46 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2022-11-11 11:51:46 +0100 |
| commit | 40d5566d56c125fc044b3849d86778780fc4516e (patch) | |
| tree | 9a984511bbaad8eac74a93ba2b496422a863f3f7 /full-adder/full-adder.srcs/sim_1 | |
| parent | 9ceab8dbefe658b9938b0ed12b50492304fcce3a (diff) | |
feedback week 1 half verwerkt
Diffstat (limited to 'full-adder/full-adder.srcs/sim_1')
| -rw-r--r-- | full-adder/full-adder.srcs/sim_1/add4b_tb.vhd | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd index 312cf22..e5e548c 100644 --- a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd +++ b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd @@ -48,6 +48,7 @@ begin for I in 0 to 255 loop Test_case <= Std_logic_vector(to_unsigned(I,8)); + wait for 1 ps; A(0) <= Test_case(0); A(1) <= Test_case(1); A(2) <= Test_case(2); |