move all vhd files to src folder

2 files changed, 2 insertions, 157 deletions

diff --git a/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
index a8d3ba8..d9536ef 100644..120000
--- a/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
+++ b/adder-and-display/adder-and-display.srcs/sim_1/bin2bcd_tb.vhd
@@ -1,80 +1 @@
-library ieee;
-library unisim;
-
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use unisim.vcomponents.all;
-
-entity bin2bcd_tb is 
-end bin2bcd_tb;
-
-architecture Behavioral of bin2bcd_tb is
-component bin2bcd port(
-	I: in std_logic_vector(4 downto 0);
-	X: out std_logic_vector(3 downto 0);
-	Y: out std_logic_vector(3 downto 0));
-end component;
--- test input
-signal I: std_logic_vector(4 downto 0) := (others => '0');
--- test output
-signal X: std_logic_vector(3 downto 0);
-signal Y: std_logic_vector(3 downto 0);
-
-signal test_case: std_logic_vector(4 downto 0);
-signal OK: boolean := true;
-begin
-	test: bin2bcd port map(
-		I => I,
-		X => X,
-		Y => Y);
-
-	tb: process
-		variable I_t: integer := 0;
-		-- expected output
-		variable X_t: integer := 0;
-		variable Y_t: integer := 0;
-	begin
-	
-	for test_i in 0 to 31 loop
-		test_case <= std_logic_vector(to_unsigned(test_i,5));
-		wait for 1 ps;
-
-		I <= test_case;
-		I_t := test_i;
-
-		case I_t is
-			when 0 | 10 | 20 | 30 => X_t := 0;
-			when 1 | 11 | 21 | 31 => X_t := 1;
-			when 2 | 12 | 22  => X_t := 2;
-			when 3 | 13 | 23  => X_t := 3;
-			when 4 | 14 | 24  => X_t := 4;
-			when 5 | 15 | 25  => X_t := 5;
-			when 6 | 16 | 26  => X_t := 6;
-			when 7 | 17 | 27  => X_t := 7;
-			when 8 | 18 | 28  => X_t := 8;
-			when 9 | 19 | 29  => X_t := 9;
-			when others => X_t := 0;
-		end case;
-		case I_t is
-			when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 => Y_t := 0;
-			when 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 => Y_t := 1;
-			when 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 => Y_t := 2;
-			when 30 | 31 => Y_t := 3;
-			when others => Y_t := 0;
-		end case;
-
-		wait for 5 ns;
-
-		if X /= std_logic_vector(to_unsigned(X_t,4)) then
-			OK <= false;
-		end if;
-		if Y /= std_logic_vector(to_unsigned(Y_t,4)) then
-			OK <= false;
-		end if;
-
-		wait for 5 ns;
-	end loop;
-	wait; -- stop simulator
-	end process;
-end Behavioral;
-
+../../../src/bin2bcd_tb.vhd
\ No newline at end of file
diff --git a/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd
index 2c8d6f5..af4506e 100644..120000
--- a/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd
+++ b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd
@@ -1,77 +1 @@
-library IEEE;
-library UNISIM;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity dispdrv_tb is
-end dispdrv_tb;
-
-architecture Behavioral of dispdrv_tb is
-component dispdrv port (
-	CLK: in std_logic;
-	D0: in std_logic_vector(7 downto 0);
-	D1: in std_logic_vector(7 downto 0);
-	D2: in std_logic_vector(7 downto 0);
-	D3: in std_logic_vector(7 downto 0);
-	D: out std_logic_vector(7 downto 0);
-	S: out std_logic_vector(1 downto 0));
-end component;
-signal CLK: std_logic;
-signal D0: std_logic_vector(7 downto 0);
-signal D1: std_logic_vector(7 downto 0);
-signal D2: std_logic_vector(7 downto 0);
-signal D3: std_logic_vector(7 downto 0);
-signal D: std_logic_vector(7 downto 0);
-signal S: std_logic_vector(1 downto 0);
-
-signal test_case: std_logic_vector(1 downto 0);
-signal OK: boolean := true;
-begin
-	test: dispdrv port map(
-		CLK => CLK,
-		D0 => D0,
-		D1 => D1,
-		D2 => D2,
-		D3 => D3,
-		D => D,
-		S => S);
-
-	tb: process
-		variable D0_t: std_logic_vector(7 downto 0) := b"00001111";
-		variable D1_t: std_logic_vector(7 downto 0) := b"11110000";
-		variable D2_t: std_logic_vector(7 downto 0) := b"01010101";
-		variable D3_t: std_logic_vector(7 downto 0) := b"10101010";
-	begin
-
-	D0 <= D0_t;
-	D1 <= D1_t;
-	D2 <= D2_t;
-	D3 <= D3_t;
-
-	for test_i in 0 to 3 loop
-		test_case <= std_logic_vector(to_unsigned(test_i, 2));
-		CLK <= '0';
-		wait for 5 ns;
-		CLK <= '1';
-		wait for 5 ns;
-
-		if test_case = 0 and D /= D0_t then
-			OK <= false;
-		end if;
-		if test_case = 1 and D /= D1_t then
-			OK <= false;
-		end if;
-		if test_case = 2 and D /= D2_t then
-			OK <= false;
-		end if;
-		if test_case = 3 and D /= D3_t then
-			OK <= false;
-		end if;
-	end loop;
-	wait;
-	end process;
-end Behavioral;
-
+../../../src/dispdrv_tb.vhd
\ No newline at end of file