Merge branch 'master' into dev

6 files changed, 167 insertions, 84 deletions

diff --git a/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd
new file mode 100644
index 0000000..18f05eb
--- /dev/null
+++ b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd
@@ -0,0 +1,72 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity add1b_tb is
+end add1b_tb;
+
+architecture behavioral of add1b_tb is
+component add1b
+port (
+	A: in std_logic;
+	B: in std_logic;
+	Cin: in std_logic;
+	X: out std_logic;
+	Cout: out std_logic);
+end component;
+
+signal A: std_logic;
+signal B: std_logic;
+signal Cin: std_logic;
+signal X: std_logic;
+signal Cout: std_logic;
+signal test_case: std_logic_vector(2 downto 0);
+signal ok: boolean := true;
+
+begin
+	test_port: add1b port map(
+		A => A,
+		B => B,
+		X => X,
+		Cout => Cout,
+		Cin => Cin);
+
+	tb: process
+		variable A_t: std_logic;
+		variable B_t: std_logic;
+		variable Cin_t: std_logic;
+		variable X_t: std_logic;
+		variable Cout_t: std_logic;
+		variable Out_t: std_logic_vector(1 downto 0);
+
+	begin
+		for i in 0 to 7 loop
+			test_case <= std_logic_vector(to_unsigned(i,3));
+			wait for 1 ps;
+	
+			A <= test_case(0);
+			B <= test_case(1);
+			Cin <= test_case(2);
+
+			A_t := test_case(0);
+			B_t := test_case(1);
+			Cin_t := test_case(2);
+
+			X_t := A_t xor B_t xor Cin_t;
+			Cout_t := (A_t and B_t) or (B_t and Cin_t) or (Cin_t and A_t);
+
+			wait for 5 ns;
+			If X /= X_t then
+				OK <= false;
+			end if;
+			if Cout /= Cout_t then
+				OK <= false;
+			end if;
+			wait for 5 ns;
+		end loop;
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
index 312cf22..e5e548c 100644
--- a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
+++ b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
@@ -48,6 +48,7 @@ begin
 		for I in 0 to 255 loop
 
 			Test_case <= Std_logic_vector(to_unsigned(I,8));
+			wait for 1 ps;
 			A(0) <= Test_case(0);
 			A(1) <= Test_case(1);
 			A(2) <= Test_case(2);
diff --git a/full-adder/full-adder.srcs/sources_1/add1b.vhd b/full-adder/full-adder.srcs/sources_1/add1b.vhd
new file mode 100644
index 0000000..a2d4068
--- /dev/null
+++ b/full-adder/full-adder.srcs/sources_1/add1b.vhd
@@ -0,0 +1,43 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- full adder entity
+entity add1b is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    Cin: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end add1b;
+
+architecture Behavioral of add1b is
+  signal s0: std_logic;
+  signal s1: std_logic;
+  signal s2: std_logic;
+  component half_add
+	port (
+	  A: in std_logic;
+      B: in std_logic;
+      X: out std_logic;
+      Cout: out std_logic);
+  end component;
+begin
+	-- first add A and B with HA
+	add0: component half_add
+    port map (
+      A => A,
+      B => B,
+      X => s0,
+      Cout => s1);
+	-- then add first result with Cin to get final result
+  add1: component half_add
+    port map (
+      A => Cin,
+      B => s0,
+      X => X,
+      Cout => s2);
+	-- calculate Cout by OR-ing the Cout of both half adders
+  Cout <= (s2 OR s1);
+end Behavioral;
diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd
index e70862b..07e5a22 100644
--- a/full-adder/full-adder.srcs/sources_1/add4b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd
@@ -2,66 +2,6 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
 
--- half adder entity
-entity half_add is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end half_add;
-
-architecture Behavioral of half_add is
-begin
-  Cout <= (A AND B);
-  X <= (A XOR B);
-end Behavioral;
-
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full adder entity
-entity add1b is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    Cin: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end add1b;
-
-architecture Behavioral of add1b is
-  signal s0: std_logic;
-  signal s1: std_logic;
-  signal s2: std_logic;
-begin
-	-- first add A and B with HA
-  add0: entity work.half_add
-    port map (
-      A => A,
-      B => B,
-      X => s0,
-      Cout => s1);
-	-- then add first result with Cin to get final result
-  add1: entity work.half_add
-    port map (
-      A => Cin,
-      B => s0,
-      X => X,
-      Cout => s2);
-	-- calculate Cout by OR-ing the Cout of both half adders
-  Cout <= (s2 OR s1);
-end Behavioral;
-
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
 -- full 4-bit adder entity
 entity add4b is
   port (
@@ -76,30 +16,38 @@ architecture Behavioral of add4b is
   signal C0: std_logic; -- Cout0 -> Cin1
   signal C1: std_logic; -- Cout1 -> Cin2
   signal C2: std_logic; -- Cout2 -> Cin3
+  component add1b 
+    port (
+      A: in std_logic;
+      B: in std_logic;
+      Cin: in std_logic;
+      X: out std_logic;
+      Cout: out std_logic);
+  end component;
 begin
 	-- full adder ladder (e.g. Cin -> Cin0, Cout0 -> Cin1, ..., Cout3 -> Cout)
-  add0: entity work.add1b
+  add0: component add1b
     port map (
       A => A(0),
       B => B(0),
       Cin => Cin,
       X => X(0),
       Cout => C0);
-  add1: entity work.add1b
+  add1: component add1b
     port map (
       A => A(1),
       B => B(1),
       Cin => C0,
       X => X(1),
       Cout => C1);
-  add2: entity work.add1b
+  add2: component add1b
     port map (
       A => A(2),
       B => B(2),
       Cin => C1,
       X => X(2),
       Cout => C2);
-  add3: entity work.add1b
+  add3: component add1b
     port map (
       A => A(3),
       B => B(3),
diff --git a/full-adder/full-adder.srcs/sources_1/half_add.vhd b/full-adder/full-adder.srcs/sources_1/half_add.vhd
new file mode 100644
index 0000000..d2d340a
--- /dev/null
+++ b/full-adder/full-adder.srcs/sources_1/half_add.vhd
@@ -0,0 +1,18 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- half adder entity
+entity half_add is
+  port (
+    A: in std_logic;
+    B: in std_logic;
+    X: out std_logic;
+    Cout: out std_logic);
+end half_add;
+
+architecture Behavioral of half_add is
+begin
+  Cout <= (A AND B);
+  X <= (A XOR B);
+end Behavioral;
diff --git a/full-adder/full-adder.xpr b/full-adder/full-adder.xpr
index 4fcc50a..7da21b3 100644
--- a/full-adder/full-adder.xpr
+++ b/full-adder/full-adder.xpr
@@ -42,8 +42,7 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -59,7 +58,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="2"/>
+    <Option Name="WTXSimLaunchSim" Val="11"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -90,13 +89,19 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sources_1/add4b.vhd">
+      <File Path="$PSRCDIR/sources_1/add1b.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sim_1/add4b_tb.vhd">
+      <File Path="$PSRCDIR/sources_1/half_add.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/add4b.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -104,7 +109,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="add4b_tb"/>
+        <Option Name="TopModule" Val="add4b"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
@@ -123,12 +128,17 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sim_1/add1b_tb.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="add4b_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopArchitecture" Val="behavioral"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -141,14 +151,6 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/add4b.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -176,11 +178,12 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/add4b.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
@@ -203,9 +206,7 @@
       <RQSFiles/>
     </Run>
   </Runs>
-  <Board>
-    <Jumpers/>
-  </Board>
+  <Board/>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">