Changes due to the refactoring of STM32-base.

4 files changed, 85 insertions, 13 deletions

diff --git a/.gitignore b/.gitignore
index 99e62ac..a31252b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,3 @@
 STM32-base
 bin
-sobj
+obj
diff --git a/README.md b/README.md
index 1fccee0..31e0b6f 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,3 @@
 # STM32-base F0 template
 
-This repository contains a template for starting projects based on the STM32F0 series devices using the [STM32-base repository](https://github.com/ThomasGravekamp/STM32-base). The code found in this repository has been tested with a STM32F030x4 device.
-
-## Usage
-
-To use this template, clone the [STM32-base repository](https://github.com/ThomasGravekamp/STM32-base) either directly in this templates folder or create a symbolic link to it.
+This repository is a project template for using a STM32F0 device with the STM32-base project. See the [STM32-base repository](https://github.com/ThomasGravekamp/STM32-base) for more information on how to get started with this template repository.
diff --git a/src/STM32F0xx_init.c b/src/STM32F0xx_init.c
new file mode 100644
index 0000000..904d9c0
--- /dev/null
+++ b/src/STM32F0xx_init.c
@@ -0,0 +1,82 @@
+#include "STM32F0xx.h"

+#include "common.h"

+

+/**

+ * Initialize the HSI clock source and reset the PLL configuration. This

+ * function is called by the startup_common.s file, just before calling the

+ * main() function.

+ */

+void SystemInit (void) {

+  // Set HSION bit

+  RCC->CR |= (uint32_t)0x00000001U;

+

+#if defined (STM32F051x8) || \

+    defined (STM32F058x8)

+  // Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits

+  RCC->CFGR &= (uint32_t)0xF8FFB80CU;

+#else

+  // Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits

+  RCC->CFGR &= (uint32_t)0x08FFB80CU;

+#endif

+

+  // Reset HSEON, CSSON and PLLON bits

+  RCC->CR &= (uint32_t)0xFEF6FFFFU;

+

+  // Reset HSEBYP bit

+  RCC->CR &= (uint32_t)0xFFFBFFFFU;

+

+  // Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits

+  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;

+

+  // Reset PREDIV[3:0] bits

+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;

+

+#if defined (STM32F072xB) || \

+    defined (STM32F078xx)

+  // Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;

+

+#elif defined (STM32F071xB)

+  // Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;

+

+#elif defined (STM32F091xC) || \

+      defined (STM32F098xx)

+  // Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;

+

+#elif defined (STM32F030x6) || \

+      defined (STM32F030x8) || \

+      defined (STM32F031x6) || \

+      defined (STM32F038xx) || \

+      defined (STM32F030xC)

+  // Reset USART1SW[1:0], I2C1SW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;

+

+#elif defined (STM32F051x8) || \

+      defined (STM32F058xx)

+  // Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;

+

+#elif defined (STM32F042x6) || \

+      defined (STM32F048xx)

+  // Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;

+

+#elif defined (STM32F070x6) || \

+      defined (STM32F070xB)

+  // Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits

+  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;

+  // Set default USB clock to PLLCLK, since there is no HSI48

+  RCC->CFGR3 |= (uint32_t)0x00000080U;

+

+#else

+  #warning "No target selected"

+#endif

+

+  // Reset HSI14 bit

+  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;

+

+  // Disable all interrupts

+  RCC->CIR = 0x00000000U;

+}

diff --git a/src/main.c b/src/main.c
index e9a7b77..f0708bd 100644
--- a/src/main.c
+++ b/src/main.c
@@ -1,4 +1,4 @@
-#include <stm32f0xx.h>
+#include "STM32F0xx.h"
 
 // Quick and dirty delay
 static void delay (unsigned int time) {
@@ -12,12 +12,6 @@ int main (void) {
 
     // Put pin in general purpose output mode (B01)
     GPIOA->MODER |= GPIO_MODER_MODER4_0;
-    // Set the output type to push pull (B0 = default)
-    // GPIOA->OTYPER = ~GPIO_OTYPER_OT_4;
-    // Set the output speed to low (B00 = default)
-    // GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR4;
-    // Set the pull up/down resistors (B00 = default)
-    // GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR4;
 
     while (1) {
         // Reset the bit for port A4