1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
|
/*
Copyright 2016-2017 StapleButter
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#ifndef ARM_H
#define ARM_H
#include "types.h"
#include "NDS.h"
#include "CP15.h"
// lame
#define C_S(x) x
#define C_N(x) x
#define C_I(x) x
#define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n))))
class ARM
{
public:
ARM(u32 num);
~ARM(); // destroy shit
void Reset();
void JumpTo(u32 addr, bool restorecpsr = false);
void RestoreCPSR();
void Halt(u32 halt)
{
if (halt==2 && Halted==1) return;
Halted = halt;
}
void CheckIRQ()
{
if (!(NDS::IME[Num] & 0x1)) return;
if (NDS::IF[Num] & NDS::IE[Num])
{
TriggerIRQ();
}
}
s32 Execute();
bool CheckCondition(u32 code)
{
if (code == 0xE) return true;
if (ConditionTable[code] & (1 << (CPSR>>28))) return true;
return false;
}
void SetC(bool c)
{
if (c) CPSR |= 0x20000000;
else CPSR &= ~0x20000000;
}
void SetNZ(bool n, bool z)
{
CPSR &= ~0xC0000000;
if (n) CPSR |= 0x80000000;
if (z) CPSR |= 0x40000000;
}
void SetNZCV(bool n, bool z, bool c, bool v)
{
CPSR &= ~0xF0000000;
if (n) CPSR |= 0x80000000;
if (z) CPSR |= 0x40000000;
if (c) CPSR |= 0x20000000;
if (v) CPSR |= 0x10000000;
}
void UpdateMode(u32 oldmode, u32 newmode);
void TriggerIRQ();
u16 CodeRead16(u32 addr)
{
u16 val;
// TODO eventually: on ARM9, THUMB opcodes are prefetched with 32bit reads
if (!Num)
{
if (!CP15::HandleCodeRead16(addr, &val))
val = NDS::ARM9Read16(addr);
}
else
val = NDS::ARM7Read16(addr);
Cycles += Waitstates[0][(addr>>24)&0xF];
return val;
}
u32 CodeRead32(u32 addr)
{
u32 val;
if (!Num)
{
if (!CP15::HandleCodeRead32(addr, &val))
val = NDS::ARM9Read32(addr);
}
else
val = NDS::ARM7Read32(addr);
Cycles += Waitstates[1][(addr>>24)&0xF];
return val;
}
u8 DataRead8(u32 addr, u32 forceuser=0)
{
u8 val;
if (!Num)
{
if (!CP15::HandleDataRead8(addr, &val, forceuser))
val = NDS::ARM9Read8(addr);
}
else
val = NDS::ARM7Read8(addr);
Cycles += Waitstates[2][(addr>>24)&0xF];
return val;
}
u16 DataRead16(u32 addr, u32 forceuser=0)
{
u16 val;
addr &= ~1;
if (!Num)
{
if (!CP15::HandleDataRead16(addr, &val, forceuser))
val = NDS::ARM9Read16(addr);
}
else
val = NDS::ARM7Read16(addr);
Cycles += Waitstates[2][(addr>>24)&0xF];
return val;
}
u32 DataRead32(u32 addr, u32 forceuser=0)
{
u32 val;
addr &= ~3;
if (!Num)
{
if (!CP15::HandleDataRead32(addr, &val, forceuser))
val = NDS::ARM9Read32(addr);
}
else
val = NDS::ARM7Read32(addr);
Cycles += Waitstates[3][(addr>>24)&0xF];
return val;
}
void DataWrite8(u32 addr, u8 val, u32 forceuser=0)
{
if (!Num)
{
if (!CP15::HandleDataWrite8(addr, val, forceuser))
NDS::ARM9Write8(addr, val);
}
else
NDS::ARM7Write8(addr, val);
Cycles += Waitstates[2][(addr>>24)&0xF];
}
void DataWrite16(u32 addr, u16 val, u32 forceuser=0)
{
addr &= ~1;
if (!Num)
{
if (!CP15::HandleDataWrite16(addr, val, forceuser))
NDS::ARM9Write16(addr, val);
}
else
NDS::ARM7Write16(addr, val);
Cycles += Waitstates[2][(addr>>24)&0xF];
}
void DataWrite32(u32 addr, u32 val, u32 forceuser=0)
{
addr &= ~3;
if (!Num)
{
if (!CP15::HandleDataWrite32(addr, val, forceuser))
NDS::ARM9Write32(addr, val);
}
else
NDS::ARM7Write32(addr, val);
Cycles += Waitstates[3][(addr>>24)&0xF];
}
u32 Num;
// waitstates:
// 0=code16 1=code32 2=data16 3=data32
// TODO eventually: nonsequential waitstates
s32 Waitstates[4][16];
s32 Cycles;
s32 CyclesToRun;
u32 Halted;
u32 R[16]; // heh
u32 CPSR;
u32 R_FIQ[8]; // holding SPSR too
u32 R_SVC[3];
u32 R_ABT[3];
u32 R_IRQ[3];
u32 R_UND[3];
u32 CurInstr;
u32 NextInstr[2];
u32 ExceptionBase;
static u32 ConditionTable[16];
u32 debug;
};
namespace ARMInterpreter
{
void A_UNK(ARM* cpu);
void T_UNK(ARM* cpu);
}
#endif // ARM_H
|