blob: 15b994880563a9bf0bd7bcfd72dc9bb10baf63b5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
/*
Copyright 2016-2017 StapleButter
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#ifndef ARMINTERPRETER_ALU_H
#define ARMINTERPRETER_ALU_H
namespace ARMInterpreter
{
#define A_PROTO_ALU_OP(x) \
\
void A_##x##_IMM(ARM* cpu); \
void A_##x##_REG_LSL_IMM(ARM* cpu); \
void A_##x##_REG_LSR_IMM(ARM* cpu); \
void A_##x##_REG_ASR_IMM(ARM* cpu); \
void A_##x##_REG_ROR_IMM(ARM* cpu); \
void A_##x##_REG_LSL_REG(ARM* cpu); \
void A_##x##_REG_LSR_REG(ARM* cpu); \
void A_##x##_REG_ASR_REG(ARM* cpu); \
void A_##x##_REG_ROR_REG(ARM* cpu); \
void A_##x##_IMM_S(ARM* cpu); \
void A_##x##_REG_LSL_IMM_S(ARM* cpu); \
void A_##x##_REG_LSR_IMM_S(ARM* cpu); \
void A_##x##_REG_ASR_IMM_S(ARM* cpu); \
void A_##x##_REG_ROR_IMM_S(ARM* cpu); \
void A_##x##_REG_LSL_REG_S(ARM* cpu); \
void A_##x##_REG_LSR_REG_S(ARM* cpu); \
void A_##x##_REG_ASR_REG_S(ARM* cpu); \
void A_##x##_REG_ROR_REG_S(ARM* cpu);
#define A_PROTO_ALU_TEST(x) \
\
void A_##x##_IMM(ARM* cpu); \
void A_##x##_REG_LSL_IMM(ARM* cpu); \
void A_##x##_REG_LSR_IMM(ARM* cpu); \
void A_##x##_REG_ASR_IMM(ARM* cpu); \
void A_##x##_REG_ROR_IMM(ARM* cpu); \
void A_##x##_REG_LSL_REG(ARM* cpu); \
void A_##x##_REG_LSR_REG(ARM* cpu); \
void A_##x##_REG_ASR_REG(ARM* cpu); \
void A_##x##_REG_ROR_REG(ARM* cpu);
A_PROTO_ALU_OP(AND)
A_PROTO_ALU_OP(EOR)
A_PROTO_ALU_OP(SUB)
A_PROTO_ALU_OP(RSB)
A_PROTO_ALU_OP(ADD)
A_PROTO_ALU_OP(ADC)
A_PROTO_ALU_OP(SBC)
A_PROTO_ALU_OP(RSC)
A_PROTO_ALU_TEST(TST)
A_PROTO_ALU_TEST(TEQ)
A_PROTO_ALU_TEST(CMP)
A_PROTO_ALU_TEST(CMN)
A_PROTO_ALU_OP(ORR)
A_PROTO_ALU_OP(MOV)
A_PROTO_ALU_OP(BIC)
A_PROTO_ALU_OP(MVN)
void A_MUL(ARM* cpu);
void A_MLA(ARM* cpu);
void A_UMULL(ARM* cpu);
void A_UMLAL(ARM* cpu);
void A_SMULL(ARM* cpu);
void A_SMLAL(ARM* cpu);
void A_CLZ(ARM* cpu);
void T_LSL_IMM(ARM* cpu);
void T_LSR_IMM(ARM* cpu);
void T_ASR_IMM(ARM* cpu);
void T_ADD_REG_(ARM* cpu);
void T_SUB_REG_(ARM* cpu);
void T_ADD_IMM_(ARM* cpu);
void T_SUB_IMM_(ARM* cpu);
void T_MOV_IMM(ARM* cpu);
void T_CMP_IMM(ARM* cpu);
void T_ADD_IMM(ARM* cpu);
void T_SUB_IMM(ARM* cpu);
void T_AND_REG(ARM* cpu);
void T_EOR_REG(ARM* cpu);
void T_LSL_REG(ARM* cpu);
void T_LSR_REG(ARM* cpu);
void T_ASR_REG(ARM* cpu);
void T_ADC_REG(ARM* cpu);
void T_SBC_REG(ARM* cpu);
void T_ROR_REG(ARM* cpu);
void T_TST_REG(ARM* cpu);
void T_NEG_REG(ARM* cpu);
void T_CMP_REG(ARM* cpu);
void T_CMN_REG(ARM* cpu);
void T_ORR_REG(ARM* cpu);
void T_MUL_REG(ARM* cpu);
void T_BIC_REG(ARM* cpu);
void T_MVN_REG(ARM* cpu);
void T_ADD_HIREG(ARM* cpu);
void T_CMP_HIREG(ARM* cpu);
void T_MOV_HIREG(ARM* cpu);
void T_ADD_PCREL(ARM* cpu);
void T_ADD_SPREL(ARM* cpu);
void T_ADD_SP(ARM* cpu);
}
#endif
|