| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | jit: fix RSC | RSDuck | 2020-06-16 |
| * | jit: fix thumb hi reg alu and mcr halt | RSDuck | 2020-06-16 |
| * | jit: decrease blockcache AddrMapping size for ARM9 | RSDuck | 2020-06-16 |
| * | jit: fix misc static branch things | RSDuck | 2020-06-16 |
| * | jit: LDM/STM keep proper stack alignment | RSDuck | 2020-06-16 |
| * | jit: fix BLX_reg with rn=lr | RSDuck | 2020-06-16 |
| * | jit: add compile option | RSDuck | 2020-06-16 |
| * | jit: make everything configurable | RSDuck | 2020-06-16 |
| * | jit: fix linux | RSDuck | 2020-06-16 |
| * | jit: fix wrongly placed const | RSDuck | 2020-06-16 |
| * | jit: SMULL and SMLAL | RSDuck | 2020-06-16 |
| * | jit: LDM/STM finally(!) working + MUL, MLA and CLZ | RSDuck | 2020-06-16 |
| * | jit: branch instructions | RSDuck | 2020-06-16 |
| * | jit: thumb block transfer working | RSDuck | 2020-06-16 |
| * | JIT: most mem instructions working | RSDuck | 2020-06-16 |
| * | JIT: compilation of word load and store | RSDuck | 2020-06-16 |
| * | jit: correct cycle counting for thumb shift by reg | RSDuck | 2020-06-16 |
| * | JIT: implemented most ALU instructions | RSDuck | 2020-06-16 |
| * | JIT: base | RSDuck | 2020-06-16 |