diff options
Diffstat (limited to 'src/CP15.cpp')
| -rw-r--r-- | src/CP15.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/CP15.cpp b/src/CP15.cpp index c1f46bc..f232bec 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -20,6 +20,7 @@ #include <string.h> #include "NDS.h" #include "ARM.h" +#include "ARMJIT.h" // access timing for cached regions @@ -811,6 +812,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val) { DataCycles = 1; *(u8*)&ITCM[addr & 0x7FFF] = val; + ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL; return; } if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) @@ -832,6 +834,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val) { DataCycles = 1; *(u16*)&ITCM[addr & 0x7FFF] = val; + ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL; return; } if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) @@ -853,6 +856,8 @@ void ARMv5::DataWrite32(u32 addr, u32 val) { DataCycles = 1; *(u32*)&ITCM[addr & 0x7FFF] = val; + ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL; + ARMJIT::cache.ARM9_ITCM[((addr + 2) & 0x7FFF) >> 1] = NULL; return; } if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) @@ -874,6 +879,8 @@ void ARMv5::DataWrite32S(u32 addr, u32 val) { DataCycles += 1; *(u32*)&ITCM[addr & 0x7FFF] = val; + ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2] = NULL; + ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2 + 1] = NULL; return; } if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) |