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-rw-r--r--ARMInterpreter.cpp9
-rw-r--r--CP15.cpp109
-rw-r--r--CP15.h15
-rw-r--r--NDS.cpp121
-rw-r--r--NDS.h3
-rw-r--r--melonDS.depend16
6 files changed, 264 insertions, 9 deletions
diff --git a/ARMInterpreter.cpp b/ARMInterpreter.cpp
index 9fd89d7..936c860 100644
--- a/ARMInterpreter.cpp
+++ b/ARMInterpreter.cpp
@@ -1,5 +1,6 @@
#include <stdio.h>
#include "NDS.h"
+#include "CP15.h"
#include "ARMInterpreter.h"
#include "ARMInterpreter_ALU.h"
#include "ARMInterpreter_Branch.h"
@@ -132,14 +133,14 @@ s32 A_MRS(ARM* cpu)
s32 A_MCR(ARM* cpu)
{
u32 cp = (cpu->CurInstr >> 8) & 0xF;
- u32 op = (cpu->CurInstr >> 21) & 0x7;
+ //u32 op = (cpu->CurInstr >> 21) & 0x7;
u32 cn = (cpu->CurInstr >> 16) & 0xF;
u32 cm = cpu->CurInstr & 0xF;
u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
if (cpu->Num==0 && cp==15)
{
- printf("CP15: R%d -> %d,%d,%d\n", (cpu->CurInstr>>12)&0xF, cn, cm, cpinfo);
+ CP15::Write((cn<<8)|(cm<<4)|cpinfo, cpu->R[(cpu->CurInstr>>12)&0xF]);
}
else
{
@@ -152,14 +153,14 @@ s32 A_MCR(ARM* cpu)
s32 A_MRC(ARM* cpu)
{
u32 cp = (cpu->CurInstr >> 8) & 0xF;
- u32 op = (cpu->CurInstr >> 21) & 0x7;
+ //u32 op = (cpu->CurInstr >> 21) & 0x7;
u32 cn = (cpu->CurInstr >> 16) & 0xF;
u32 cm = cpu->CurInstr & 0xF;
u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
if (cpu->Num==0 && cp==15)
{
- printf("CP15: R%d <- %d,%d,%d\n", (cpu->CurInstr>>12)&0xF, cn, cm, cpinfo);
+ cpu->R[(cpu->CurInstr>>12)&0xF] = CP15::Read((cn<<8)|(cm<<4)|cpinfo);
}
else
{
diff --git a/CP15.cpp b/CP15.cpp
new file mode 100644
index 0000000..5b86b9a
--- /dev/null
+++ b/CP15.cpp
@@ -0,0 +1,109 @@
+#include <stdio.h>
+#include "NDS.h"
+
+namespace CP15
+{
+
+u32 Control;
+
+u32 DTCMSetting, ITCMSetting;
+
+
+void Reset()
+{
+ Control = 0x78; // dunno
+
+ DTCMSetting = 0;
+ ITCMSetting = 0;
+}
+
+
+void UpdateDTCMSetting()
+{
+ if (Control & (1<<16))
+ {
+ NDS::ARM9DTCMBase = DTCMSetting & 0xFFFFF000;
+ NDS::ARM9DTCMSize = 256 << (DTCMSetting & 0x3E);
+ printf("DTCM enabled at %08X, size %X\n", NDS::ARM9DTCMBase, NDS::ARM9DTCMSize);
+ }
+ else
+ {
+ NDS::ARM9DTCMBase = 0xFFFFFFFF;
+ NDS::ARM9DTCMSize = 0;
+ printf("DTCM disabled\n");
+ }
+}
+
+void UpdateITCMSetting()
+{
+ if (Control & (1<<18))
+ {
+ NDS::ARM9ITCMSize = 256 << (DTCMSetting & 0x3E);
+ printf("ITCM enabled at %08X, size %X\n", 0, NDS::ARM9DTCMSize);
+ }
+ else
+ {
+ NDS::ARM9ITCMSize = 0;
+ printf("ITCM disabled\n");
+ }
+}
+
+
+void Write(u32 id, u32 val)
+{
+ switch (id)
+ {
+ case 0x100:
+ val &= 0x000FF085;
+ Control &= ~0x000FF085;
+ Control |= val;
+ UpdateDTCMSetting();
+ UpdateITCMSetting();
+ return;
+
+
+ case 0x910:
+ DTCMSetting = val;
+ UpdateDTCMSetting();
+ return;
+ case 0x911:
+ ITCMSetting = val;
+ UpdateITCMSetting();
+ return;
+ }
+}
+
+u32 Read(u32 id)
+{
+ switch (id)
+ {
+ case 0x000: // CPU ID
+ case 0x003:
+ case 0x004:
+ case 0x005:
+ case 0x006:
+ case 0x007:
+ return 0x41059461;
+
+ case 0x001:
+ // cache type. todo
+ return 0;
+
+ case 0x002: // TCM size
+ return (6 << 6) | (5 << 18);
+
+
+ case 0x100: // control reg
+ return Control;
+
+
+ case 0x910:
+ return DTCMSetting;
+ case 0x911:
+ return ITCMSetting;
+ }
+
+ return 0;
+}
+
+}
diff --git a/CP15.h b/CP15.h
new file mode 100644
index 0000000..c633327
--- /dev/null
+++ b/CP15.h
@@ -0,0 +1,15 @@
+
+#ifndef CP15_H
+#define CP15_H
+
+namespace CP15
+{
+
+void Reset();
+
+void Write(u32 id, u32 val);
+u32 Read(u32 id);
+
+}
+
+#endif
diff --git a/NDS.cpp b/NDS.cpp
index ed573cb..7cf00b0 100644
--- a/NDS.cpp
+++ b/NDS.cpp
@@ -2,6 +2,7 @@
#include <string.h>
#include "NDS.h"
#include "ARM.h"
+#include "CP15.h"
namespace NDS
@@ -16,8 +17,17 @@ u8 ARM9BIOS[0x1000];
u8 ARM7BIOS[0x4000];
u8 MainRAM[0x400000];
+
u8 ARM7WRAM[0x10000];
+u8 ARM9ITCM[0x8000];
+u32 ARM9ITCMSize;
+u8 ARM9DTCM[0x4000];
+u32 ARM9DTCMBase, ARM9DTCMSize;
+
+// IO shit
+u16 IPCSync9, IPCSync7;
+
bool Running;
@@ -59,9 +69,19 @@ void Reset()
memset(MainRAM, 0, 0x400000);
memset(ARM7WRAM, 0, 0x10000);
+ memset(ARM9ITCM, 0, 0x8000);
+ memset(ARM9DTCM, 0, 0x4000);
+
+ ARM9ITCMSize = 0;
+ ARM9DTCMBase = 0xFFFFFFFF;
+ ARM9DTCMSize = 0;
+
+ IPCSync9 = 0;
+ IPCSync7 = 0;
ARM9->Reset();
ARM7->Reset();
+ CP15::Reset();
ARM9Cycles = 0;
ARM7Cycles = 0;
@@ -99,6 +119,14 @@ u8 ARM9Read8(u32 addr)
{
return *(u8*)&ARM9BIOS[addr & 0xFFF];
}
+ if (addr < ARM9ITCMSize)
+ {
+ return *(u8*)&ARM9ITCM[addr & 0x7FFF];
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ return *(u8*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF];
+ }
switch (addr & 0xFF000000)
{
@@ -116,11 +144,25 @@ u16 ARM9Read16(u32 addr)
{
return *(u16*)&ARM9BIOS[addr & 0xFFF];
}
+ if (addr < ARM9ITCMSize)
+ {
+ return *(u16*)&ARM9ITCM[addr & 0x7FFF];
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ return *(u16*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF];
+ }
switch (addr & 0xFF000000)
{
case 0x02000000:
return *(u16*)&MainRAM[addr & 0x3FFFFF];
+
+ case 0x04000000:
+ switch (addr)
+ {
+ case 0x04000180: return IPCSync9;
+ }
}
printf("unknown arm9 read16 %08X\n", addr);
@@ -133,6 +175,14 @@ u32 ARM9Read32(u32 addr)
{
return *(u32*)&ARM9BIOS[addr & 0xFFF];
}
+ if (addr < ARM9ITCMSize)
+ {
+ return *(u32*)&ARM9ITCM[addr & 0x7FFF];
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ return *(u32*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF];
+ }
switch (addr & 0xFF000000)
{
@@ -146,6 +196,17 @@ u32 ARM9Read32(u32 addr)
void ARM9Write8(u32 addr, u8 val)
{
+ if (addr < ARM9ITCMSize)
+ {
+ *(u8*)&ARM9ITCM[addr & 0x7FFF] = val;
+ return;
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ *(u8*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF] = val;
+ return;
+ }
+
switch (addr & 0xFF000000)
{
case 0x02000000:
@@ -158,11 +219,37 @@ void ARM9Write8(u32 addr, u8 val)
void ARM9Write16(u32 addr, u16 val)
{
+ if (addr < ARM9ITCMSize)
+ {
+ *(u16*)&ARM9ITCM[addr & 0x7FFF] = val;
+ return;
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ *(u16*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF] = val;
+ return;
+ }
+
switch (addr & 0xFF000000)
{
case 0x02000000:
*(u16*)&MainRAM[addr & 0x3FFFFF] = val;
return;
+
+ case 0x04000000:
+ switch (addr)
+ {
+ case 0x04000180:
+ IPCSync7 &= 0xFFF0;
+ IPCSync7 |= ((val & 0x0F00) >> 8);
+ IPCSync9 &= 0xB0FF;
+ IPCSync9 |= (val & 0x4F00);
+ if ((val & 0x2000) && (IPCSync7 & 0x4000))
+ {
+ printf("ARM9 IPCSYNC IRQ TODO\n");
+ }
+ return;
+ }
}
printf("unknown arm9 write16 %08X %04X\n", addr, val);
@@ -170,6 +257,17 @@ void ARM9Write16(u32 addr, u16 val)
void ARM9Write32(u32 addr, u32 val)
{
+ if (addr < ARM9ITCMSize)
+ {
+ *(u32*)&ARM9ITCM[addr & 0x7FFF] = val;
+ return;
+ }
+ if (addr >= ARM9DTCMBase && addr < (ARM9DTCMBase + ARM9DTCMSize))
+ {
+ *(u32*)&ARM9DTCM[(addr - ARM9DTCMBase) & 0x3FFF] = val;
+ return;
+ }
+
switch (addr & 0xFF000000)
{
case 0x02000000:
@@ -177,7 +275,7 @@ void ARM9Write32(u32 addr, u32 val)
return;
}
- printf("unknown arm9 write32 %08X %08X\n", addr, val);
+ printf("unknown arm9 write32 %08X %08X | %08X\n", addr, val, ARM9->R[15]);
}
@@ -216,6 +314,12 @@ u16 ARM7Read16(u32 addr)
case 0x03800000:
return *(u16*)&ARM7WRAM[addr & 0xFFFF];
+
+ case 0x04000000:
+ switch (addr)
+ {
+ case 0x04000180: return IPCSync7;
+ }
}
printf("unknown arm7 read16 %08X\n", addr);
@@ -269,6 +373,21 @@ void ARM7Write16(u32 addr, u16 val)
case 0x03800000:
*(u16*)&ARM7WRAM[addr & 0xFFFF] = val;
return;
+
+ case 0x04000000:
+ switch (addr)
+ {
+ case 0x04000180:
+ IPCSync9 &= 0xFFF0;
+ IPCSync9 |= ((val & 0x0F00) >> 8);
+ IPCSync7 &= 0xB0FF;
+ IPCSync7 |= (val & 0x4F00);
+ if ((val & 0x2000) && (IPCSync9 & 0x4000))
+ {
+ printf("ARM7 IPCSYNC IRQ TODO\n");
+ }
+ return;
+ }
}
printf("unknown arm7 write16 %08X %04X\n", addr, val);
diff --git a/NDS.h b/NDS.h
index 2d30135..0649042 100644
--- a/NDS.h
+++ b/NDS.h
@@ -7,6 +7,9 @@
namespace NDS
{
+extern u32 ARM9ITCMSize;
+extern u32 ARM9DTCMBase, ARM9DTCMSize;
+
void Init();
void Reset();
diff --git a/melonDS.depend b/melonDS.depend
index 2925585..7309cf0 100644
--- a/melonDS.depend
+++ b/melonDS.depend
@@ -3,16 +3,17 @@
<stdio.h>
"NDS.h"
-1480030849 c:\documents\sources\melonds\nds.h
+1480776639 c:\documents\sources\melonds\nds.h
"types.h"
1463409689 c:\documents\sources\melonds\types.h
-1480767942 source:c:\documents\sources\melonds\nds.cpp
+1480776984 source:c:\documents\sources\melonds\nds.cpp
<stdio.h>
<string.h>
"NDS.h"
"ARM.h"
+ "CP15.h"
1480772238 source:c:\documents\sources\melonds\arm.cpp
<stdio.h>
@@ -30,9 +31,10 @@
"types.h"
"ARM.h"
-1480736379 source:c:\documents\sources\melonds\arminterpreter.cpp
+1480776855 source:c:\documents\sources\melonds\arminterpreter.cpp
<stdio.h>
"NDS.h"
+ "CP15.h"
"ARMInterpreter.h"
"ARMInterpreter_ALU.h"
"ARMInterpreter_Branch.h"
@@ -47,7 +49,7 @@
1480774402 c:\documents\sources\melonds\arminterpreter_alu.h
-1480730662 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
+1480774326 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
"ARM.h"
1480771004 c:\documents\sources\melonds\arminterpreter_loadstore.h
@@ -55,3 +57,9 @@
1480770968 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
"ARM.h"
+1480776964 c:\documents\sources\melonds\cp15.h
+
+1480777799 source:c:\documents\sources\melonds\cp15.cpp
+ <stdio.h>
+ "NDS.h"
+