diff options
| -rw-r--r-- | src/ARM.cpp | 17 | ||||
| -rw-r--r-- | src/ARM.h | 11 | ||||
| -rw-r--r-- | src/DMA.cpp | 19 | ||||
| -rw-r--r-- | src/NDS.cpp | 3 |
4 files changed, 38 insertions, 12 deletions
diff --git a/src/ARM.cpp b/src/ARM.cpp index d71d0e1..226b463 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -48,6 +48,8 @@ ARM::ARM(u32 num) // well uh Num = num; + SetClockShift(0); // safe default + for (int i = 0; i < 16; i++) { Waitstates[0][i] = 1; @@ -432,18 +434,9 @@ s32 ARM::Execute() } } - if (Num==0) - { - s32 diff = Cycles - lastcycles; - NDS::RunTimingCriticalDevices(0, diff >> 1); - lastcycles = Cycles - (diff&1); - } - else - { - s32 diff = Cycles - lastcycles; - NDS::RunTimingCriticalDevices(1, diff); - lastcycles = Cycles; - } + s32 diff = Cycles - lastcycles; + NDS::RunTimingCriticalDevices(Num, diff >> ClockShift); + lastcycles = Cycles - (diff & ClockDiffMask); // TODO optimize this shit!!! if (Halted) @@ -38,6 +38,12 @@ public: void Reset(); + void SetClockShift(u32 shift) + { + ClockShift = shift; + ClockDiffMask = (1<<shift) - 1; + } + void DoSavestate(Savestate* file); void JumpTo(u32 addr, bool restorecpsr = false); @@ -227,6 +233,11 @@ public: u32 Num; + // shift relative to system clock + // 0=33MHz 1=66MHz 2=133MHz + u32 ClockShift; + u32 ClockDiffMask; + // waitstates: // 0=code16 1=code32 2=data16 3=data32 // TODO eventually: nonsequential waitstates diff --git a/src/DMA.cpp b/src/DMA.cpp index f0c22b5..e88814e 100644 --- a/src/DMA.cpp +++ b/src/DMA.cpp @@ -26,6 +26,25 @@ // NOTES ON DMA SHIT // // * could use optimized code paths for common types of DMA transfers. for example, VRAM +// have to profile it to see if it's actually worth doing + + +// DMA TIMINGS +// +// sequential timing: +// * 1 cycle per read or write +// * in 32bit mode, accessing a 16bit bus (mainRAM, palette, VRAM) incurs 1 cycle of penalty +// * in 32bit mode, transferring from mainRAM to another bank is 1 cycle faster +// * if source and destination are the same memory bank, there is a 1 cycle penalty +// * transferring from mainRAM to mainRAM is a trainwreck (all accesses are made nonsequential) +// +// nonsequential timing: +// * nonseq penalty is applied to the first read and write +// * I also figure it gets nonseq penalty again when resuming, after having been interrupted by +// another DMA (TODO: check) +// * applied to all accesses for mainRAM->mainRAM, resulting in timings of 16-18 cycles per unit +// +// TODO: GBA slot DMA::DMA(u32 cpu, u32 num) diff --git a/src/NDS.cpp b/src/NDS.cpp index 77810ee..32deeb6 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -345,6 +345,9 @@ void Reset() SPI::Reset(); RTC::Reset(); Wifi::Reset(); + + ARM9->SetClockShift(1); + ARM7->SetClockShift(0); } void Stop() |