diff options
| -rw-r--r-- | src/ARM.h | 2 | ||||
| -rw-r--r-- | src/ARMJIT.cpp | 22 | ||||
| -rw-r--r-- | src/CP15.cpp | 53 |
3 files changed, 41 insertions, 36 deletions
@@ -269,7 +269,7 @@ public: // for aarch64 JIT they need to go up here // to be addressable by a 12-bit immediate u32 ITCMSize; - u32 DTCMBase, DTCMSize; + u32 DTCMBase, DTCMMask, DTCMSize; s32 RegionCodeCycles; u8 ITCM[ITCMPhysicalSize]; diff --git a/src/ARMJIT.cpp b/src/ARMJIT.cpp index ffde5f9..029c334 100644 --- a/src/ARMJIT.cpp +++ b/src/ARMJIT.cpp @@ -179,8 +179,8 @@ T SlowRead9(u32 addr, ARMv5* cpu) T val; if (addr < cpu->ITCMSize) val = *(T*)&cpu->ITCM[addr & 0x7FFF]; - else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize)) - val = *(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF]; + else if ((addr & cpu->DTCMMask) == cpu->DTCMBase) + val = *(T*)&cpu->DTCM[addr & 0x3FFF]; else if (std::is_same<T, u32>::value) val = (ConsoleType == 0 ? NDS::ARM9Read32 : DSi::ARM9Read32)(addr); else if (std::is_same<T, u16>::value) @@ -204,9 +204,9 @@ void SlowWrite9(u32 addr, ARMv5* cpu, u32 val) CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); *(T*)&cpu->ITCM[addr & 0x7FFF] = val; } - else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize)) + else if ((addr & cpu->DTCMMask) == cpu->DTCMBase) { - *(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF] = val; + *(T*)&cpu->DTCM[addr & 0x3FFF] = val; } else if (std::is_same<T, u32>::value) { @@ -377,7 +377,7 @@ bool DecodeLiteral(bool thumb, const FetchedInstr& instr, u32& addr) return false; } -bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink, u32 lr, bool& link, +bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink, u32 lr, bool& link, u32& linkAddr, u32& targetAddr) { if (thumb) @@ -420,7 +420,7 @@ bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink linkAddr = instr.Addr + 4; cond = instr.Cond(); - if (instr.Info.Kind == ARMInstrInfo::ak_BL + if (instr.Info.Kind == ARMInstrInfo::ak_BL || instr.Info.Kind == ARMInstrInfo::ak_B) { s32 offset = (s32)(instr.Instr << 8) >> 6; @@ -461,7 +461,7 @@ bool IsIdleLoop(bool thumb, FetchedInstr* instrs, int instrsCount) u16 dstRegs = instrs[i].Info.DstRegs & ~(1 << 15); regsDisallowedToWrite |= srcRegs & ~regsWrittenTo; - + if (dstRegs & regsDisallowedToWrite) return false; regsWrittenTo |= dstRegs; @@ -551,7 +551,7 @@ InterpreterFunc InterpretTHUMB[ARMInstrInfo::tk_Count] = F(LDRB_IMM), F(STRH_IMM), F(LDRH_IMM), F(STR_SPREL), F(LDR_SPREL), F(PUSH), F(POP), F(LDMIA), F(STMIA), F(BCOND), F(BX), F(BLX_REG), F(B), F(BL_LONG_1), F(BL_LONG_2), - F(UNK), F(SVC), + F(UNK), F(SVC), T_BL_LONG // BL_LONG psudo opcode }; #undef F @@ -607,7 +607,7 @@ void CompileBlock(ARM* cpu) } // some memory has been remapped - RetireJitBlock(existingBlockIt->second); + RetireJitBlock(existingBlockIt->second); map.erase(existingBlockIt); } @@ -830,7 +830,7 @@ void CompileBlock(ARM* cpu) lr = linkAddr; hasLink = true; } - + r15 = target + (thumb ? 2 : 4); assert(r15 == cpu->R[15]); @@ -940,7 +940,7 @@ void CompileBlock(ARM* cpu) block->StartAddrLocal = localAddr; FloodFillSetFlags(instrs, i - 1, 0xF); - + JitEnableWrite(); block->EntryPoint = JITCompiler->CompileBlock(cpu, thumb, instrs, i, hasMemoryInstr); JitEnableExecute(); diff --git a/src/CP15.cpp b/src/CP15.cpp index f30ed9e..1d81931 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -50,6 +50,7 @@ void ARMv5::CP15Reset() ITCMSize = 0; DTCMBase = 0xFFFFFFFF; + DTCMMask = 0; DTCMSize = 0; memset(ICache, 0, 0x2000); @@ -102,25 +103,29 @@ void ARMv5::CP15DoSavestate(Savestate* file) void ARMv5::UpdateDTCMSetting() { u32 newDTCMBase; + u32 newDTCMMask; u32 newDTCMSize; + if (CP15Control & (1<<16)) { - newDTCMBase = DTCMSetting & 0xFFFFF000; newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F); - //printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, newDTCMBase, newDTCMSize); + newDTCMMask = 0xFFFFF000 & ~(newDTCMSize-1); + newDTCMBase = DTCMSetting & newDTCMMask; } else { - newDTCMBase = 0xFFFFFFFF; newDTCMSize = 0; - //printf("DTCM disabled\n"); + newDTCMBase = 0xFFFFFFFF; + newDTCMMask = 0; } - if (newDTCMBase != DTCMBase || newDTCMSize != DTCMSize) + + if (newDTCMBase != DTCMBase || newDTCMMask != DTCMMask) { #ifdef JIT_ENABLED - ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize); + ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMMask); #endif DTCMBase = newDTCMBase; + DTCMMask = newDTCMMask; DTCMSize = newDTCMSize; } } @@ -600,12 +605,12 @@ void ARMv5::CP15Write(u32 id, u32 val) case 0x910: - DTCMSetting = val; + DTCMSetting = val & 0xFFFFF03E; UpdateDTCMSetting(); return; case 0x911: - ITCMSetting = val; + ITCMSetting = val & 0x0000003E; UpdateITCMSetting(); return; @@ -774,10 +779,10 @@ void ARMv5::DataRead8(u32 addr, u32* val) *val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)]; return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *val = *(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; + *val = *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)]; return; } @@ -797,10 +802,10 @@ void ARMv5::DataRead16(u32 addr, u32* val) *val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)]; return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *val = *(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; + *val = *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)]; return; } @@ -826,10 +831,10 @@ void ARMv5::DataRead32(u32 addr, u32* val) *val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)]; return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; + *val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)]; return; } @@ -847,10 +852,10 @@ void ARMv5::DataRead32S(u32 addr, u32* val) *val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)]; return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles += 1; - *val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; + *val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)]; return; } @@ -871,10 +876,10 @@ void ARMv5::DataWrite8(u32 addr, u8 val) #endif return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; + *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; return; } @@ -897,10 +902,10 @@ void ARMv5::DataWrite16(u32 addr, u16 val) #endif return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; + *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; return; } @@ -929,10 +934,10 @@ void ARMv5::DataWrite32(u32 addr, u32 val) #endif return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles = 1; - *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; + *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; return; } @@ -953,10 +958,10 @@ void ARMv5::DataWrite32S(u32 addr, u32 val) #endif return; } - if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) + if ((addr & DTCMMask) == DTCMBase) { DataCycles += 1; - *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; + *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; return; } |