more complete (and accurate) CP15 setup for direct boot

5 files changed, 72 insertions, 12 deletions

diff --git a/src/ARM.cpp b/src/ARM.cpp
index bdb10bf..1abdbdd 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -162,6 +162,8 @@ void ARMv5::Reset()
         GetMemRegion = NDS::ARM9GetMemRegion;
     }
 
+    //PU_Map = PU_PrivMap;
+
     ARM::Reset();
 }
 
@@ -225,10 +227,22 @@ void ARM::DoSavestate(Savestate* file)
 
     if (!file->Saving)
     {
+        CPSR |= 0x00000010;
+        R_FIQ[7] |= 0x00000010;
+        R_SVC[2] |= 0x00000010;
+        R_ABT[2] |= 0x00000010;
+        R_IRQ[2] |= 0x00000010;
+        R_UND[2] |= 0x00000010;
+
         if (!Num)
         {
             SetupCodeMem(R[15]); // should fix it
             ((ARMv5*)this)->RegionCodeCycles = ((ARMv5*)this)->MemTimings[R[15] >> 12][0];
+
+            /*if ((CPSR & 0x1F) == 0x10)
+                ((ARMv5*)this)->PU_Map = ((ARMv5*)this)->PU_UserMap;
+            else
+                ((ARMv5*)this)->PU_Map = ((ARMv5*)this)->PU_PrivMap;*/
         }
         else
         {
@@ -415,7 +429,7 @@ void ARM::RestoreCPSR()
     UpdateMode(oldcpsr, CPSR);
 }
 
-void ARM::UpdateMode(u32 oldmode, u32 newmode)
+void ARM::UpdateMode(u32 oldmode, u32 newmode, bool phony)
 {
     if ((oldmode & 0x1F) == (newmode & 0x1F)) return;
 
@@ -485,13 +499,12 @@ void ARM::UpdateMode(u32 oldmode, u32 newmode)
         break;
     }
 
-    if (Num == 0)
+    if ((!phony) && (Num == 0))
     {
         /*if ((newmode & 0x1F) == 0x10)
             ((ARMv5*)this)->PU_Map = ((ARMv5*)this)->PU_UserMap;
         else
             ((ARMv5*)this)->PU_Map = ((ARMv5*)this)->PU_PrivMap;*/
-        //if ((newmode & 0x1F) == 0x10) printf("!! USER MODE\n");
     }
 }
 
diff --git a/src/ARM.h b/src/ARM.h
index 71de8f8..dd88f7d 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -93,7 +93,7 @@ public:
         if (v) CPSR |= 0x10000000;
     }
 
-    void UpdateMode(u32 oldmode, u32 newmode);
+    void UpdateMode(u32 oldmode, u32 newmode, bool phony = false);
 
     void TriggerIRQ();
 
@@ -294,6 +294,7 @@ public:
 
     // games operate under system mode, generally
     #define PU_Map PU_PrivMap
+    //u8* PU_Map;
 
     // code/16N/32N/32S
     u8 MemTimings[0x100000][4];
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 6d43b62..1c81900 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -410,7 +410,7 @@ void A_LDM(ARM* cpu)
     }
 
     if ((cpu->CurInstr & (1<<22)) && !(cpu->CurInstr & (1<<15)))
-        cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10);
+        cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10, true);
 
     for (int i = 0; i < 15; i++)
     {
@@ -439,7 +439,7 @@ void A_LDM(ARM* cpu)
     }
 
     if ((cpu->CurInstr & (1<<22)) && !(cpu->CurInstr & (1<<15)))
-        cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR);
+        cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR, true);
 
     if (cpu->CurInstr & (1<<21))
     {
@@ -494,7 +494,7 @@ void A_STM(ARM* cpu)
         else if (mode != 0x10 && mode != 0x1F)
             isbanked = (baseid >= 13 && baseid < 15);
 
-        cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10);
+        cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10, true);
     }
 
     for (u32 i = 0; i < 16; i++)
@@ -520,7 +520,7 @@ void A_STM(ARM* cpu)
     }
 
     if (cpu->CurInstr & (1<<22))
-        cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR);
+        cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR, true);
 
     if ((cpu->CurInstr & (1<<23)) && (cpu->CurInstr & (1<<21)))
         cpu->R[baseid] = base;
diff --git a/src/DSi.cpp b/src/DSi.cpp
index d453ee2..eb702d0 100644
--- a/src/DSi.cpp
+++ b/src/DSi.cpp
@@ -499,6 +499,31 @@ void SetupDirectBoot()
     NDS::ARM7BIOSProt = 0x20;
 
     SPI_Firmware::SetupDirectBoot(true);
+
+    ARM9->CP15Write(0x100, 0x00056078);
+    ARM9->CP15Write(0x200, 0x0000004A);
+    ARM9->CP15Write(0x201, 0x0000004A);
+    ARM9->CP15Write(0x300, 0x0000000A);
+    ARM9->CP15Write(0x502, 0x15111011);
+    ARM9->CP15Write(0x503, 0x05101011);
+    ARM9->CP15Write(0x600, 0x04000033);
+    ARM9->CP15Write(0x601, 0x04000033);
+    ARM9->CP15Write(0x610, 0x02000031);
+    ARM9->CP15Write(0x611, 0x02000031);
+    ARM9->CP15Write(0x620, 0x00000000);
+    ARM9->CP15Write(0x621, 0x00000000);
+    ARM9->CP15Write(0x630, 0x08000033);
+    ARM9->CP15Write(0x631, 0x08000033);
+    ARM9->CP15Write(0x640, 0x0E00001B);
+    ARM9->CP15Write(0x641, 0x0E00001B);
+    ARM9->CP15Write(0x650, 0x00000000);
+    ARM9->CP15Write(0x651, 0x00000000);
+    ARM9->CP15Write(0x660, 0xFFFF001D);
+    ARM9->CP15Write(0x661, 0xFFFF001D);
+    ARM9->CP15Write(0x670, 0x02FFC01B);
+    ARM9->CP15Write(0x671, 0x02FFC01B);
+    ARM9->CP15Write(0x910, 0x0E00000A);
+    ARM9->CP15Write(0x911, 0x00000020);
 }
 
 void SoftReset()
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 2bf724f..97983ab 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -414,11 +414,32 @@ void SetupDirectBoot()
         ARM7BIOSProt = 0x1204;
 
         SPI_Firmware::SetupDirectBoot(false);
-    }
 
-    ARM9->CP15Write(0x910, 0x0300000A);
-    ARM9->CP15Write(0x911, 0x00000020);
-    ARM9->CP15Write(0x100, ARM9->CP15Read(0x100) | 0x00050000);
+        ARM9->CP15Write(0x100, 0x00012078);
+        ARM9->CP15Write(0x200, 0x00000042);
+        ARM9->CP15Write(0x201, 0x00000042);
+        ARM9->CP15Write(0x300, 0x00000002);
+        ARM9->CP15Write(0x502, 0x15111011);
+        ARM9->CP15Write(0x503, 0x05100011);
+        ARM9->CP15Write(0x600, 0x04000033);
+        ARM9->CP15Write(0x601, 0x04000033);
+        ARM9->CP15Write(0x610, 0x0200002B);
+        ARM9->CP15Write(0x611, 0x0200002B);
+        ARM9->CP15Write(0x620, 0x00000000);
+        ARM9->CP15Write(0x621, 0x00000000);
+        ARM9->CP15Write(0x630, 0x08000035);
+        ARM9->CP15Write(0x631, 0x08000035);
+        ARM9->CP15Write(0x640, 0x0300001B);
+        ARM9->CP15Write(0x641, 0x0300001B);
+        ARM9->CP15Write(0x650, 0x00000000);
+        ARM9->CP15Write(0x651, 0x00000000);
+        ARM9->CP15Write(0x660, 0xFFFF001D);
+        ARM9->CP15Write(0x661, 0xFFFF001D);
+        ARM9->CP15Write(0x670, 0x027FF017);
+        ARM9->CP15Write(0x671, 0x027FF017);
+        ARM9->CP15Write(0x910, 0x0300000A);
+        ARM9->CP15Write(0x911, 0x00000020);
+    }
 
     ARM9->R[12] = NDSCart::Header.ARM9EntryAddress;
     ARM9->R[13] = 0x03002F7C;