diff options
| author | Dario Nieuwenhuis <dirbaio@dirbaio.net> | 2018-05-24 00:58:36 +0200 | 
|---|---|---|
| committer | Dario Nieuwenhuis <dirbaio@dirbaio.net> | 2018-05-24 01:09:23 +0200 | 
| commit | cb79a5dc14ad2c259636101cc99ae6fe082ef609 (patch) | |
| tree | 55bae5ed586205a27a2d02faf9bb00a1797eb1b5 /src | |
| parent | 20050fb66886f96b38e0cb14ac147434b638005d (diff) | |
Make Main RAM size configurable in a single place.
Diffstat (limited to 'src')
| -rw-r--r-- | src/NDS.cpp | 28 | ||||
| -rw-r--r-- | src/NDS.h | 4 | 
2 files changed, 17 insertions, 15 deletions
| diff --git a/src/NDS.cpp b/src/NDS.cpp index fa7cb84..bdb0c2d 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -57,7 +57,7 @@ u32 CPUStop;  u8 ARM9BIOS[0x1000];  u8 ARM7BIOS[0x4000]; -u8 MainRAM[0x400000]; +u8 MainRAM[MAIN_RAM_SIZE];  u8 SharedWRAM[0x8000];  u8 WRAMCnt; @@ -281,7 +281,7 @@ void Reset()          fclose(f);      } -    memset(MainRAM, 0, 0x400000); +    memset(MainRAM, 0, MAIN_RAM_SIZE);      memset(SharedWRAM, 0, 0x8000);      memset(ARM7WRAM, 0, 0x10000); @@ -918,7 +918,7 @@ u8 ARM9Read8(u32 addr)      switch (addr & 0xFF000000)      {      case 0x02000000: -        return *(u8*)&MainRAM[addr & 0x3FFFFF]; +        return *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM9) return *(u8*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask]; @@ -967,7 +967,7 @@ u16 ARM9Read16(u32 addr)      switch (addr & 0xFF000000)      {      case 0x02000000: -        return *(u16*)&MainRAM[addr & 0x3FFFFF]; +        return *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM9) return *(u16*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask]; @@ -1016,7 +1016,7 @@ u32 ARM9Read32(u32 addr)      switch (addr & 0xFF000000)      {      case 0x02000000: -        return *(u32*)&MainRAM[addr & 0x3FFFFF]; +        return *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM9) return *(u32*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask]; @@ -1060,7 +1060,7 @@ void ARM9Write8(u32 addr, u8 val)      switch (addr & 0xFF000000)      {      case 0x02000000: -        *(u8*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -1085,7 +1085,7 @@ void ARM9Write16(u32 addr, u16 val)      switch (addr & 0xFF000000)      {      case 0x02000000: -        *(u16*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -1124,7 +1124,7 @@ void ARM9Write32(u32 addr, u32 val)      switch (addr & 0xFF000000)      {      case 0x02000000: -        *(u32*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -1176,7 +1176,7 @@ u8 ARM7Read8(u32 addr)      {      case 0x02000000:      case 0x02800000: -        return *(u8*)&MainRAM[addr & 0x3FFFFF]; +        return *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM7) return *(u8*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask]; @@ -1213,7 +1213,7 @@ u16 ARM7Read16(u32 addr)      {      case 0x02000000:      case 0x02800000: -        return *(u16*)&MainRAM[addr & 0x3FFFFF]; +        return *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM7) return *(u16*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask]; @@ -1253,7 +1253,7 @@ u32 ARM7Read32(u32 addr)      {      case 0x02000000:      case 0x02800000: -        return *(u32*)&MainRAM[addr & 0x3FFFFF]; +        return *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)];      case 0x03000000:          if (SWRAM_ARM7) return *(u32*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask]; @@ -1283,7 +1283,7 @@ void ARM7Write8(u32 addr, u8 val)      {      case 0x02000000:      case 0x02800000: -        *(u8*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -1314,7 +1314,7 @@ void ARM7Write16(u32 addr, u16 val)      {      case 0x02000000:      case 0x02800000: -        *(u16*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -1349,7 +1349,7 @@ void ARM7Write32(u32 addr, u32 val)      {      case 0x02000000:      case 0x02800000: -        *(u32*)&MainRAM[addr & 0x3FFFFF] = val; +        *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val;          return;      case 0x03000000: @@ -101,7 +101,9 @@ extern u8 ROMSeed1[2*8];  extern u8 ARM9BIOS[0x1000];  extern u8 ARM7BIOS[0x4000]; -extern u8 MainRAM[0x400000]; +#define MAIN_RAM_SIZE 0x400000 + +extern u8 MainRAM[MAIN_RAM_SIZE];  bool Init();  void DeInit(); |