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authorNadia Holmquist Pedersen <nadia@nhp.sh>2022-11-05 22:37:27 +0100
committerNadia Holmquist Pedersen <nadia@nhp.sh>2022-11-05 22:37:27 +0100
commit9a5e88491344cc3e53547b447f37156a514f9a24 (patch)
tree357ec2bd830d5fa0e8687502e9d2fa0500eb2d51 /src/dolphin
parentc387fb18192e9c33dea12eaae3b7f4883a13139a (diff)
JIT: Add bits for Windows ARM64 support
Diffstat (limited to 'src/dolphin')
-rw-r--r--src/dolphin/Arm64Emitter.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/dolphin/Arm64Emitter.cpp b/src/dolphin/Arm64Emitter.cpp
index 47e97b1..c42d4d4 100644
--- a/src/dolphin/Arm64Emitter.cpp
+++ b/src/dolphin/Arm64Emitter.cpp
@@ -16,6 +16,10 @@
#include "../types.h"
#include "MathUtil.h"
+#ifdef _WIN32
+ #include <windows.h>
+#endif
+
#ifdef __APPLE__
#include <libkern/OSCacheControl.h>
#endif
@@ -392,6 +396,8 @@ void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
#if defined(__APPLE__)
// Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
+#elif defined(_WIN32)
+ FlushInstructionCache(GetCurrentProcess(), start, end - start);
#else
// Don't rely on GCC's __clear_cache implementation, as it caches
// icache/dcache cache line sizes, that can vary between cores on