diff options
| author | WaluigiWare64 <68647953+WaluigiWare64@users.noreply.github.com> | 2020-10-23 00:39:29 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-23 00:39:29 +0100 |
| commit | 8d70d0926c6307368398a894cbebfbdc0f538194 (patch) | |
| tree | 72774a626ff8a30850c36eba33fdac38962739cb /src/dolphin/Arm64Emitter.h | |
| parent | a8851a51f19577f153a3fa5d1021be5794f0921a (diff) | |
| parent | 65be1840f02a7499fa08178abcefddfefec6d9b0 (diff) | |
Merge branch 'master' into feature/zip-support
Diffstat (limited to 'src/dolphin/Arm64Emitter.h')
| -rw-r--r-- | src/dolphin/Arm64Emitter.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dolphin/Arm64Emitter.h b/src/dolphin/Arm64Emitter.h index 4c49502..3da3912 100644 --- a/src/dolphin/Arm64Emitter.h +++ b/src/dolphin/Arm64Emitter.h @@ -727,7 +727,7 @@ public: void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift); void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift); void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift); - void ROR_(ARM64Reg Rd, ARM64Reg Rm, int shift); + void ROR(ARM64Reg Rd, ARM64Reg Rm, int shift); // Logical (immediate) void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false); |