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| author | Arisotura <thetotalworm@gmail.com> | 2021-10-28 19:45:32 +0200 |
|---|---|---|
| committer | Arisotura <thetotalworm@gmail.com> | 2021-10-28 19:45:32 +0200 |
| commit | 9d82826cdb84aa5e261d6a55e42812652e6ab13f (patch) | |
| tree | 4174270113508614abb2968b2ce91159e3bffaa2 /src/GPU3D_Soft.h | |
| parent | ae489d9e033ae22b56bb99bd44d23423320ab874 (diff) | |
fix some gaps in CPU modes
* non-defined CPU modes are actually possible
* bit4 of all PSRs is forced to one (modes 00-0F aren't possible)
* modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks)
* modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
Diffstat (limited to 'src/GPU3D_Soft.h')
0 files changed, 0 insertions, 0 deletions