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authorRSDuck <rsduck@users.noreply.github.com>2020-06-30 23:50:41 +0200
committerRSDuck <rsduck@users.noreply.github.com>2020-06-30 23:50:41 +0200
commitc5381d2911d47fb1fcbd6ec27a83f5da3606c4bd (patch)
tree1dbf9eb1bbe418d14f07dc3a0e30821fb5deb258 /src/CP15.cpp
parentea6d03581b689738d0d1930b28d1588019cf4077 (diff)
reconcile DSi and JIT, fastmem for x64 and Windows
Diffstat (limited to 'src/CP15.cpp')
-rw-r--r--src/CP15.cpp21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 3d64259..992c83f 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -608,6 +608,27 @@ void ARMv5::CP15Write(u32 id, u32 val)
ITCMSetting = val;
UpdateITCMSetting();
return;
+
+ case 0xF00:
+ //printf("cache debug index register %08X\n", val);
+ return;
+
+ case 0xF10:
+ //printf("cache debug instruction tag %08X\n", val);
+ return;
+
+ case 0xF20:
+ //printf("cache debug data tag %08X\n", val);
+ return;
+
+ case 0xF30:
+ //printf("cache debug instruction cache %08X\n", val);
+ return;
+
+ case 0xF40:
+ //printf("cache debug data cache %08X\n", val);
+ return;
+
}
if ((id&0xF00)!=0x700)