diff options
| author | Jesse Talavera-Greenberg <jesse@jesse.tg> | 2023-11-18 10:40:54 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-18 16:40:54 +0100 |
| commit | 544fefa27f698f3a0d799a782dc03d3eb47561db (patch) | |
| tree | b4907fca30677cc4e1befb02301392f172eed543 /src/CP15.cpp | |
| parent | f2d7a290156b5aa62edc00644c55b00de73b6229 (diff) | |
Refactor the JIT to be object-oriented (#1879)
* Move TinyVector to a new file
- So it's less sensitive to #include ordering
* Forgot to include assert.h
* Refactor ARMJIT_Memory into an object
* Oops, forgot a declaration
* Refactor ARMJIT to be contained in an object
* Remove an unused function declaration
* Add a missing #include
* Remove a now-unused global
* Use ARMJIT_Memory's own memory access functions
* Fix some omissions in the ARM JIT
* Move libandroid to be a member of ARMJIT_Memory instead of a global
* Default-initialize most fields in ARMJIT_Compiler.h
* Define NOOP_IF_NO_JIT
* Finish refactoring the JIT to be object-oriented
Diffstat (limited to 'src/CP15.cpp')
| -rw-r--r-- | src/CP15.cpp | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/src/CP15.cpp b/src/CP15.cpp index b8a77e2..e8d8c1a 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -22,11 +22,8 @@ #include "DSi.h" #include "ARM.h" #include "Platform.h" - -#ifdef JIT_ENABLED -#include "ARMJIT.h" #include "ARMJIT_Memory.h" -#endif +#include "ARMJIT.h" using Platform::Log; using Platform::LogLevel; @@ -125,9 +122,7 @@ void ARMv5::UpdateDTCMSetting() if (newDTCMBase != DTCMBase || newDTCMMask != DTCMMask) { -#ifdef JIT_ENABLED - ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize); -#endif + JIT.Memory.RemapDTCM(newDTCMBase, newDTCMSize); DTCMBase = newDTCMBase; DTCMMask = newDTCMMask; } @@ -926,9 +921,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val) { DataCycles = 1; *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; -#ifdef JIT_ENABLED - ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); -#endif + JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); return; } if ((addr & DTCMMask) == DTCMBase) @@ -958,9 +951,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val) { DataCycles = 1; *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; -#ifdef JIT_ENABLED - ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); -#endif + JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); return; } if ((addr & DTCMMask) == DTCMBase) @@ -990,9 +981,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val) { DataCycles = 1; *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; -#ifdef JIT_ENABLED - ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); -#endif + JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); return; } if ((addr & DTCMMask) == DTCMBase) @@ -1015,7 +1004,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val) DataCycles += 1; *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; #ifdef JIT_ENABLED - ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); + JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); #endif return; } |