JIT: base

all instructions are interpreted

1 files changed, 54 insertions, 0 deletions

diff --git a/src/ARMJIT_x64/ARMJIT_Compiler.h b/src/ARMJIT_x64/ARMJIT_Compiler.h
new file mode 100644
index 0000000..8e1d100
--- /dev/null
+++ b/src/ARMJIT_x64/ARMJIT_Compiler.h
@@ -0,0 +1,54 @@
+#ifndef ARMJIT_COMPILER_H
+#define ARMJIT_COMPILER_H
+
+#include "../dolphin/x64Emitter.h"
+
+#include "../ARMJIT.h"
+
+
+namespace ARMJIT
+{
+
+const Gen::X64Reg RCPU = Gen::RBP;
+const Gen::X64Reg RCycles = Gen::R14;
+const Gen::X64Reg RCPSR = Gen::R15;
+
+const Gen::X64Reg RSCRATCH = Gen::EAX;
+const Gen::X64Reg RSCRATCH2 = Gen::EDX;
+const Gen::X64Reg RSCRATCH3 = Gen::ECX;
+
+class Compiler : public Gen::X64CodeBlock
+{
+public:
+    Compiler();
+
+    CompiledBlock CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrsCount);
+
+    void StartBlock(ARM* cpu);
+    CompiledBlock FinaliseBlock();
+
+    void Compile(RegCache& regs, const FetchedInstr& instr);
+private:
+    void AddCycles_C();
+
+    Gen::OpArg Comp_ShiftRegImm(int op, int amount, Gen::X64Reg rm, bool S, bool& carryUsed);
+
+    void A_Comp_ALU(const FetchedInstr& instr);
+
+    void LoadCPSR();
+    void SaveCPSR();
+
+    bool CPSRDirty = false;
+
+    FetchedInstr CurrentInstr;
+
+    bool Thumb;
+    u32 Num;
+    u32 R15;
+
+    u32 ConstantCycles;
+};
+
+}
+
+#endif
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