aboutsummaryrefslogtreecommitdiff
path: root/src/ARMJIT_A64
diff options
context:
space:
mode:
authorWaluigiWare64 <68647953+WaluigiWare64@users.noreply.github.com>2021-01-03 15:53:23 +0000
committerGitHub <noreply@github.com>2021-01-03 15:53:23 +0000
commit83648f2d3109bf16ac6f2317ab772803af11f482 (patch)
treee8207c55c4ae052ba07713892e998ab9050e9301 /src/ARMJIT_A64
parentf070eafce473c49979cfe8ec1d2dd65de9084884 (diff)
parentcb58a422ac59f40825f7a7c2e9b75237eb04637d (diff)
Merge branch 'master' into feature/zip-support
Diffstat (limited to 'src/ARMJIT_A64')
-rw-r--r--src/ARMJIT_A64/ARMJIT_Linkage.S12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/ARMJIT_A64/ARMJIT_Linkage.S b/src/ARMJIT_A64/ARMJIT_Linkage.S
index 7886315..58b5399 100644
--- a/src/ARMJIT_A64/ARMJIT_Linkage.S
+++ b/src/ARMJIT_A64/ARMJIT_Linkage.S
@@ -8,8 +8,13 @@
.p2align 4,,15
+#ifdef __APPLE__
+.global _ARM_Dispatch
+_ARM_Dispatch:
+#else
.global ARM_Dispatch
ARM_Dispatch:
+#endif
stp x19, x20, [sp, #-96]!
stp x21, x22, [sp, #16]
stp x23, x24, [sp, #32]
@@ -25,8 +30,13 @@ ARM_Dispatch:
.p2align 4,,15
+#ifdef __APPLE__
+.global _ARM_Ret
+_ARM_Ret:
+#else
.global ARM_Ret
ARM_Ret:
+#endif
str RCycles, [RCPU, ARM_Cycles_offset]
str RCPSR, [RCPU, ARM_CPSR_offset]
@@ -65,4 +75,4 @@ ARM_RestoreContext:
ldp x17, x18, [sp, #248]
mov sp, x17
- br x18 \ No newline at end of file
+ br x18