only trigger cart DMA on the CPU for which the cart interface is enabled.

fixes unstable firmware boot.

2 files changed, 8 insertions, 3 deletions

diff --git a/src/NDS.cpp b/src/NDS.cpp
index 1329f6c..626ce3d 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -931,7 +931,7 @@ u16 ARM9Read16(u32 addr)
         return 0xFFFF;
     }
 
-    //printf("unknown arm9 read16 %08X %08X %08X %08X\n", addr, ARM9->R[15], ARM9->R[1], ARM9->R[2]);
+    //printf("unknown arm9 read16 %08X %08X\n", addr, ARM9->R[15]);
     return 0;
 }
 
diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp
index d972ffb..696666b 100644
--- a/src/NDSCart.cpp
+++ b/src/NDSCart.cpp
@@ -828,8 +828,11 @@ void ROMPrepareData(u32 param)
     DataOutPos += 4;
 
     ROMCnt |= (1<<23);
-    NDS::CheckDMAs(0, 0x05);
-    NDS::CheckDMAs(1, 0x12);
+
+    if (NDS::ExMemCnt[0] & (1<<11))
+        NDS::CheckDMAs(1, 0x12);
+    else
+        NDS::CheckDMAs(0, 0x05);
 }
 
 void WriteROMCnt(u32 val)
@@ -969,9 +972,11 @@ void WriteROMCnt(u32 val)
     // the bus is parallel with 8 bits
     // thus a command would take 8 cycles to be transferred
     // and it would take 4 cycles to receive a word of data
+    // TODO: advance read position if bit28 is set
 
     u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
     u32 cmddelay = 8 + (ROMCnt & 0x1FFF);
+    if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
 
     if (datasize == 0)
         NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*cmddelay, ROMEndTransfer, 0);