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authorStapleButter <thetotalworm@gmail.com>2017-04-25 02:26:37 +0200
committerStapleButter <thetotalworm@gmail.com>2017-04-25 02:26:37 +0200
commit9b5f293a9e9f720e7b0939cf37c413481c4e156c (patch)
tree4d869648cbdadd707d5c27bc12b18cea82abdb97
parent9eb68c2ede167cf0913dcb178981b295f47eb369 (diff)
implement leading gap and 0x200-gap delays for ROM transfers
-rw-r--r--src/NDSCart.cpp11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp
index 2593b40..cf52009 100644
--- a/src/NDSCart.cpp
+++ b/src/NDSCart.cpp
@@ -969,10 +969,12 @@ void WriteROMCnt(u32 val)
// and it would take 4 cycles to receive a word of data
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
+ u32 cmddelay = 8 + (ROMCnt & 0x1FFF);
+
if (datasize == 0)
- NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*8, ROMEndTransfer, 0);
+ NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*cmddelay, ROMEndTransfer, 0);
else
- NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*(8+4), ROMPrepareData, 0);
+ NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*(cmddelay+4), ROMPrepareData, 0);
}
u32 ReadROMData()
@@ -984,7 +986,10 @@ u32 ReadROMData()
if (DataOutPos < DataOutLen)
{
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
- NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*4, ROMPrepareData, 0);
+ u32 delay = 4;
+ if (!(DataOutPos & 0x1FF)) delay += ((ROMCnt >> 16) & 0x3F);
+
+ NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*delay, ROMPrepareData, 0);
}
else
ROMEndTransfer(0);