more sensible cache timings

(still a big fat hack)

3 files changed, 17 insertions, 6 deletions

diff --git a/src/ARM.cpp b/src/ARM.cpp
index 4ee72a3..7e2e887 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -169,8 +169,7 @@ void ARMv5::JumpTo(u32 addr, bool restorecpsr)
     u32 oldregion = R[15] >> 24;
     u32 newregion = addr >> 24;
 
-    if (addr < ITCMSize) CodeCycles = 1;
-    else                 CodeCycles = MemTimings[addr >> 12][0];
+    RegionCodeCycles = MemTimings[addr >> 12][0];
 
     s32 cycles;
 
@@ -476,7 +475,7 @@ s32 ARMv5::Execute()
             R[15] += 2;
             CurInstr = NextInstr[0];
             NextInstr[0] = NextInstr[1];
-            if (R[15] & 0x2) NextInstr[1] >>= 16;
+            if (R[15] & 0x2) { NextInstr[1] >>= 16; CodeCycles = 0; }
             else             NextInstr[1] = CodeRead32(R[15]);
 
             // actually execute
diff --git a/src/ARM.h b/src/ARM.h
index 649fe8e..9a9b03c 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -263,6 +263,8 @@ public:
 
     // code/16N/32N/32S
     u8 MemTimings[0x100000][4];
+
+    s32 RegionCodeCycles;
 };
 
 class ARMv4 : public ARM
diff --git a/src/CP15.cpp b/src/CP15.cpp
index c35e653..2187fae 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -27,8 +27,9 @@
 // this was measured to be close to hardware average
 // a value of 1 would represent a perfect cache, but that causes
 // games to run too fast, causing a number of issues
+// code cache timing can get as low as 3
 const int kDataCacheTiming = 2;
-const int kCodeCacheTiming = 2;
+const int kCodeCacheTiming = 5;
 
 
 void ARMv5::CP15Reset()
@@ -241,7 +242,7 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
 
         if (pu & 0x40)
         {
-            MemTimings[i][0] = kCodeCacheTiming;
+            MemTimings[i][0] = 0xFF;//kCodeCacheTiming;
         }
         else
         {
@@ -252,7 +253,7 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
         {
             MemTimings[i][1] = kDataCacheTiming;
             MemTimings[i][2] = kDataCacheTiming;
-            MemTimings[i][3] = kDataCacheTiming;
+            MemTimings[i][3] = 1;
         }
         else
         {
@@ -511,9 +512,18 @@ u32 ARMv5::CodeRead32(u32 addr)
 {
     if (addr < ITCMSize)
     {
+        CodeCycles = 1;
         return *(u32*)&ITCM[addr & 0x7FFF];
     }
 
+    CodeCycles = RegionCodeCycles;
+    if (CodeCycles == 0xFF)
+    {
+        // sort of code cache hit/miss average
+        if (!(addr & 0x1F)) CodeCycles = kCodeCacheTiming;
+        else                CodeCycles = 1;
+    }
+
     if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask];
 
     return NDS::ARM9Read32(addr);