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authorArisotura <thetotalworm@gmail.com>2021-05-03 14:58:45 +0200
committerArisotura <thetotalworm@gmail.com>2021-05-03 14:58:45 +0200
commit41cd092a15b3dbb9c3118124537e0481dfbaddc7 (patch)
tree252651a52446c22e22e2ff8eb201e728016801e5
parent2ff065e5eab38165b4f3380284f58bc8019d8712 (diff)
NDSCart: enforce WR bit.
Bad Apple demo will break, because its NitroFS driver is broken. it needs a DLDI argv structure to exist in order to use its DLDI driver instead.
-rw-r--r--src/NDSCart.cpp10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp
index 2b5fea0..af70cbd 100644
--- a/src/NDSCart.cpp
+++ b/src/NDSCart.cpp
@@ -1816,12 +1816,12 @@ void WriteROMCnt(u32 val)
// commands that do writes will change this
TransferDir = 0;
- // TODO: how should we detect that the transfer should be a write?
- // you're supposed to set bit30 of ROMCNT for a write, but it's also
- // possible to do reads just fine when that bit is set
if (Cart)
TransferDir = Cart->ROMCommandStart(TransferCmd, TransferData, TransferLen);
+ if ((datasize > 0) && (((ROMCnt >> 30) & 0x1) != TransferDir))
+ printf("NDSCART: !! BAD TRANSFER DIRECTION FOR CMD %02X, DIR=%d, ROMCNT=%08X\n", ROMCommand[0], TransferDir, ROMCnt);
+
ROMCnt &= ~(1<<23);
// ROM transfer timings
@@ -1869,6 +1869,8 @@ void AdvanceROMTransfer()
u32 ReadROMData()
{
+ if (ROMCnt & (1<<30)) return 0;
+
if (ROMCnt & (1<<23))
{
AdvanceROMTransfer();
@@ -1879,6 +1881,8 @@ u32 ReadROMData()
void WriteROMData(u32 val)
{
+ if (!(ROMCnt & (1<<30))) return;
+
ROMData = val;
if (ROMCnt & (1<<23))