blob: 00bf0884dccc3ae10c2fcb6a8d371c75e92c95f0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
-- vim: ft=vhdl
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.ppu_consts.all;
entity spi_tb is
end spi_tb;
architecture behavioral of spi_tb is
signal SYSCLK : std_logic := '0';
signal SPI_CLK : std_logic := '0';
signal SPI_DATA : std_logic := '0';
signal RESET : std_logic := '0';
begin
uut : entity work.spi port map(
SYSCLK => SYSCLK,
RESET => RESET,
DO => open,
DI => SPI_DATA,
SR => '0',
DCK => SPI_CLK,
WEN => open);
process
begin
while true loop
wait for 5 ns;
SYSCLK <= '1';
wait for 5 ns;
SYSCLK <= '0';
end loop;
wait; -- stop for simulator
end process;
process
begin
-- undivert(`test-background-color-spi.tb.vhd') -- m4 macro expansion (see makefile)
RESET <= '1';
wait for 50 ns;
RESET <= '0';
wait; -- stop for simulator
end process;
end;
|