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library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
entity ppu_pceg_tb is
end ppu_pceg_tb;
architecture behavioral of ppu_pceg_tb is
component ppu_pceg port(
CLK : in std_logic; -- system clock
RESET : in std_logic; -- async reset
SPRITE_BG : out std_logic; -- sprite info fetch + sprite pixel fetch
SPRITE_FG : out std_logic; -- sprite pixel fetch
DONE : out std_logic; -- last pipeline stage done
READY : out std_logic); -- rgb buffer propagation ready
end component;
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal SPRITE_BG : std_logic;
signal SPRITE_FG : std_logic;
signal DONE : std_logic;
signal READY : std_logic;
begin
uut : ppu_pceg port map(
CLK => CLK,
RESET => RESET,
SPRITE_BG => SPRITE_BG,
SPRITE_FG => SPRITE_FG,
DONE => DONE,
READY => READY);
tb : process
begin
for i in 0 to 32 loop
wait for 5 ns;
CLK <= '1';
wait for 5 ns;
CLK <= '0';
end loop;
wait; -- stop for simulator
end process;
gert : process
begin
RESET <= '1';
wait for 1 ns;
RESET <= '0';
wait for 100 ns;
RESET <= '1';
wait for 5 ns;
RESET <= '0';
wait;
end process;
end;
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