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path: root/basys3/basys3.srcs/ppu_dispctl_demo.xdc
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create_clock -period 10.000 -name CLK100 -waveform {0.000 5.000} [get_ports CLK100]
set_input_delay -clock [get_clocks CLK100] -min -add_delay 2.000 [get_ports RESET]
set_input_delay -clock [get_clocks CLK100] -max -add_delay 3.000 [get_ports RESET]
set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100]
set_property IOSTANDARD LVCMOS33 [get_ports {G[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {G[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {G[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {G[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports HSYNC]
set_property IOSTANDARD LVCMOS33 [get_ports {R[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {R[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {R[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {R[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports VSYNC]
set_property PACKAGE_PIN W5 [get_ports CLK100]
set_property PACKAGE_PIN P19 [get_ports HSYNC]
set_property PACKAGE_PIN R19 [get_ports VSYNC]


set_property PACKAGE_PIN J18 [get_ports {B[3]}]
set_property PACKAGE_PIN K18 [get_ports {B[2]}]
set_property PACKAGE_PIN L18 [get_ports {B[1]}]
set_property PACKAGE_PIN N18 [get_ports {B[0]}]
set_property PACKAGE_PIN D17 [get_ports {G[3]}]
set_property PACKAGE_PIN G17 [get_ports {G[2]}]
set_property PACKAGE_PIN H17 [get_ports {G[1]}]
set_property PACKAGE_PIN J17 [get_ports {G[0]}]
set_property PACKAGE_PIN N19 [get_ports {R[3]}]
set_property PACKAGE_PIN J19 [get_ports {R[2]}]
set_property PACKAGE_PIN H19 [get_ports {R[1]}]
set_property PACKAGE_PIN G19 [get_ports {R[0]}]

set_property PACKAGE_PIN T18 [get_ports RESET]
set_property IOSTANDARD LVCMOS33 [get_ports RESET]