From 2588df5f89da62b857287344d6a7f2cc6951e938 Mon Sep 17 00:00:00 2001
From: NielsCoding <48092678+heavydemon21@users.noreply.github.com>
Date: Wed, 15 Mar 2023 18:56:15 +0100
Subject: architecture docu
---
docs/architecture.md | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index 5001eed..94f17a4 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -1,3 +1,38 @@
+# Hooded Havic: Miniboss Mania
+
+
+# introduction
+Welcome to Hooded Havoc: Miniboss Mania, an exciting 2D platformer game created by our team Joshua, Loek, Bjorn, Frenk and Niels! This game was developed using the STM32 microcontroller as the game engine and the FPGA as the Picture Processing Unit (PPU).
+
+In Hooded Havoc: Miniboss Mania, you will take on the role of a brave hero who must battle through multiple levels filled with challenging obstacles and formidable minibosses. With smooth gameplay and engaging graphics, you will feel immersed in a world of adventure and excitement.
+
+Our use of the STM32 microcontroller and FPGA PPU allowed us to create a unique and innovative gaming experience. The STM32 provides efficient and reliable processing power, while the FPGA ensures that our graphics are rendered smoothly and accurately.
+
+So get ready to embark on a thrilling journey through Hooded Havoc: Miniboss Mania, and see how far you can make it!
+## Objective
+The objective of Hooded Havoc: Miniboss Mania is to guide the hero through multiple levels, defeating minibosses and overcoming obstacles along the way. The ultimate goal is to reach the final boss and defeat them to retrieve the stolen staff.
+
+To achieve this objective, the player must use their platforming skills to jump, run, and dodge obstacles while also battling enemies and minibosses. Each level presents a unique challenge that will require the player to adapt and strategize to overcome.
+
+As the player progresses through the game, they will unlock new abilities and power-ups that will aid them in their journey. The player must use these abilities wisely to defeat the minibosses and ultimately save the world.
+
+So, the objective of Hooded Havoc: Miniboss Mania is not only to provide an exciting and engaging gaming experience but also to challenge players to use their skills and strategic thinking to overcome obstacles and emerge victorious.
+## Problem statement
+One potential problem that could arise in the development of Hooded Havoc: Miniboss Mania is related to the PPU and communication between the STM32 and PPU.
+
+The PPU is responsible for rendering the graphics and displaying them on the screen, while the STM32 is responsible for processing the game logic and input from the player. However, if there is a problem with the communication between these two components, it could lead to synchronization issues and graphical glitches that could affect the player's experience.
+
+For example, if the PPU is unable to keep up with the processing speed of the STM32, the graphics may lag or appear distorted, causing the game to become unplayable. Similarly, if there is a delay in communication between the STM32 and PPU, it could result in a mismatch between the game logic and the displayed graphics, leading to confusion for the player.
+
+To ensure a smooth and enjoyable gaming experience, it is essential to address any potential issues with the PPU and communication between the STM32 and PPU during the development process. This may involve optimizing the code for both components, adjusting the communication protocol, or adding buffer systems to prevent lag or synchronization issues.
+### architecture ( top level)
+;
+
+
+
+
+### design document (mid-low level)
+
# General system architecture
--
cgit v1.2.3
From 2346a009fefb6e880bd7a36bb132cad833185080 Mon Sep 17 00:00:00 2001
From: NielsCoding <48092678+heavydemon21@users.noreply.github.com>
Date: Wed, 15 Mar 2023 19:46:54 +0100
Subject: bob
---
assets/TopLevel.PNG | Bin 0 -> 13919 bytes
assets/TopLevelArchi | 1 -
docs/BobSprint2.md | 19 +++++++++++++++++++
docs/architecture.md | 3 ++-
4 files changed, 21 insertions(+), 2 deletions(-)
create mode 100644 assets/TopLevel.PNG
delete mode 100644 assets/TopLevelArchi
create mode 100644 docs/BobSprint2.md
(limited to 'docs')
diff --git a/assets/TopLevel.PNG b/assets/TopLevel.PNG
new file mode 100644
index 0000000..2a7b16d
Binary files /dev/null and b/assets/TopLevel.PNG differ
diff --git a/assets/TopLevelArchi b/assets/TopLevelArchi
deleted file mode 100644
index bd8c538..0000000
--- a/assets/TopLevelArchi
+++ /dev/null
@@ -1 +0,0 @@
-zVdNc5swEP01PrYDFlD76NhpOtN0yowPSY8KbECtYD3y4o/++kpGfDuJkzp1fTG72hXSe29XYsTm2e5G8VX6DWOQo7ET70ZsMRqPXT9w9J/x7EvP1JuUjkSJ2AY1jqX4DdZp85JCxLDuBBKiJLHqOiPMc4io4+NK4bYb9oiy+9YVT2DgWEZcDr13IqbUet1g2gx8AZGk9tWT8adyIONVsN3JOuUxblsudj1ic4VI5VO2m4M04FW4lHmfnxitF6Ygp1MSvPAuyxcOfL1NQr8QyfebOPzg27XRvtowxHr/1kRFKSaYc3ndeK8UFnkMZlZHW03MLeJKO13t/AlEe0smLwi1K6VM2lG9YLW/t/kH44cxPvqVudi1Bxd7a5VrNQt8EgLrWmOhInhm38xKiasE6Jk4ryZKKxwwA70enadAchKb7jq4lVpSxzVs6AdLyCvIsYvccFnYN4WS70ENONPSWpnHIpOziFBprDagSGgZ3/IHkCGuBQnMdcgDEmGmA6QZuOLRr+TA5xylydOzscfDrzXHTIrE5JLht00kFiRFDvO69hqWTC7snudpiKtN8G3J2J7hVSW0bVWgY31pq/jcKvHsVHgDKnTDIYVSHqGjWyDbVBAsV/ygx63ukl0MzwAXG3fx8t0hXpNjcLnvBdf0om3F7bYV1vu90GUOVghKaChAnb/1BCe2HnbJ1hMM9L6MFED+32md+ZMLa72auIXVghO/OFK+00OKHemi4yNQ1fidH6rhiTZsFHk8M/c2bUWSr9ci6lX5TtB967l1ddBWU9PGeIeLg3di9brOcXJa4PtHsK98J1e5fUOIQu+k5t7rnaBBn9JynzarfWnsTdQXUcB6E5VADCY6yKPe9l8oZnjwvl4xT5wL//C6WfWIF2UTXFI1bp/s6RtV4/bl551LNdpsvpjK8Oa7k13/AQ==
\ No newline at end of file
diff --git a/docs/BobSprint2.md b/docs/BobSprint2.md
new file mode 100644
index 0000000..6fff8fc
--- /dev/null
+++ b/docs/BobSprint2.md
@@ -0,0 +1,19 @@
+
+
+# Proud of
+Simulation: We're proud of the simulation that we created to test our game because it allows us to identify and address potential issues before the game is released. This helps ensure that the game is as polished and bug-free as possible.
+
+PPU: Our use of an FPGA-based PPU (Picture Processing Unit) in our game engine allows us to achieve high-quality graphics and smooth animation. This is important because it helps create an immersive and engaging gaming experience.
+
+Upscaling: We've implemented a sophisticated upscaling that allows us to scale up our game. This Ensures that our game runs smoothly and without any
+
+Collisions: We've put a lot of effort into making sure that our collision detection system is accurate and reliable. This ensures that the game mechanics work as intended and that players are able to navigate the game world without frustration.
+
+Artwork: We're proud of the artwork that was created which is stunning and imaginative artwork that brings the game world to life. From character designs to background artwork, every aspect of the game has been given careful attention to ensure that it looks as good as it plays. And more is coming!
+# Challegens
+Upscaling: While our upscaling algorithm is sophisticated, one of the challenges we faced was synchronization. Because we're upscaling in real-time, we had to ensure that the upscaling process didn't cause any lag or delay in the game. This required careful optimization of the algorithm and synchronization with other game components.
+
+PPU: While the use of an FPGA-based PPU allowed us to achieve high-quality graphics, it also presented some challenges. Specifically, the limited resources of the FPGA required us to optimize the PPU code to ensure that it could handle the demands of real-time gameplay.
+
+Communication bug fixes on the STM32: As with any complex system, we encountered some bugs in the communication between the STM32 microcontroller and the other components of the system. This required careful debugging and troubleshooting to identify and fix the issues.
+
diff --git a/docs/architecture.md b/docs/architecture.md
index 94f17a4..d4632b5 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -25,8 +25,9 @@ The PPU is responsible for rendering the graphics and displaying them on the scr
For example, if the PPU is unable to keep up with the processing speed of the STM32, the graphics may lag or appear distorted, causing the game to become unplayable. Similarly, if there is a delay in communication between the STM32 and PPU, it could result in a mismatch between the game logic and the displayed graphics, leading to confusion for the player.
To ensure a smooth and enjoyable gaming experience, it is essential to address any potential issues with the PPU and communication between the STM32 and PPU during the development process. This may involve optimizing the code for both components, adjusting the communication protocol, or adding buffer systems to prevent lag or synchronization issues.
+
### architecture ( top level)
-;
+;
--
cgit v1.2.3
From 6a70bf52bc2ed5d28b7d08854fabfaee27be3e84 Mon Sep 17 00:00:00 2001
From: NielsCoding <48092678+heavydemon21@users.noreply.github.com>
Date: Wed, 15 Mar 2023 20:08:12 +0100
Subject: architecture and design
---
docs/architecture.md | 38 ++++++++++++++++++++++++++++++++------
1 file changed, 32 insertions(+), 6 deletions(-)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index d4632b5..cf4440f 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -26,14 +26,40 @@ For example, if the PPU is unable to keep up with the processing speed of the ST
To ensure a smooth and enjoyable gaming experience, it is essential to address any potential issues with the PPU and communication between the STM32 and PPU during the development process. This may involve optimizing the code for both components, adjusting the communication protocol, or adding buffer systems to prevent lag or synchronization issues.
-### architecture ( top level)
+# architecture ( top level)
;
-
-
-
-### design document (mid-low level)
-
+## STM32
+### game engine
+### user input
+### PPU communication
+### APU communication
+### level editing pipeline
+
+## FPGA (PPU)
+### PPU
+### SPI
+### APU
+
+## Screen
+### VGA
+
+
+# design document (mid-low level)
+## STM32
+### game engine
+### user input
+### PPU communication
+### APU communication
+### level editing pipeline
+
+## FPGA (PPU)
+### PPU
+### SPI
+### APU
+
+## Screen
+### VGA
# General system architecture
--
cgit v1.2.3
From 7b44ae05a17b544dfcddd8db322bbd916d2d2df3 Mon Sep 17 00:00:00 2001
From: lonkaars
Date: Wed, 15 Mar 2023 22:17:56 +0100
Subject: architecture document update
---
assets/ppu-level-1.svg | 2 +-
assets/ppu-level-2.svg | 2 +-
docs/architecture.md | 119 +++++++++++++++++++++++++++++++------------------
docs/ppu.drawio | 2 +-
4 files changed, 78 insertions(+), 47 deletions(-)
(limited to 'docs')
diff --git a/assets/ppu-level-1.svg b/assets/ppu-level-1.svg
index e0d1949..6b3a2ab 100644
--- a/assets/ppu-level-1.svg
+++ b/assets/ppu-level-1.svg
@@ -1,3 +1,3 @@
-
\ No newline at end of file
+
\ No newline at end of file
diff --git a/assets/ppu-level-2.svg b/assets/ppu-level-2.svg
index a7f343f..303e95a 100644
--- a/assets/ppu-level-2.svg
+++ b/assets/ppu-level-2.svg
@@ -1,3 +1,3 @@
-
\ No newline at end of file
+
\ No newline at end of file
diff --git a/docs/architecture.md b/docs/architecture.md
index 5001eed..9be6751 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -1,12 +1,35 @@
# General system architecture
-
+The existing hardware components available for building this project consists
+of:
+
+- Raspberry Pi
+- Nucleo STM32 development board
+- Basys3 FPGA development board
+- Arduino Uno R3
+
+The Raspberry Pi is by far the most powerful component out of these 4, but
+because one of the project requirements is that no general-purpose operating
+system is used, utilizing the Raspberry Pi will involve writing low-level
+drivers for its interfaces, which will likely cost a lot of effort.
+
+As to not risk project failure due to hardware constraints, the decision was
+made to use the STM32 microcontroller and FPGA in combination, as these two are
+both familiar and still relatively powerful platforms. Because audio and video
+consist of data streams that require constant output, the audio and graphics
+processing is outsourced to the FPGA. All other game logic processing such as
+world loading, or map and entity interactions is done on the STM32
+microcontroller.
+
+Our game also supports an optional second player, as is shown in the following
+diagram.
-Important notes:
+
-- Gamepad 2 is optionally connected
-- The PPU and APU are implemented on the FPGA
-- The game logic and PPU/APU control logic runs on the STM32 only
+In the above diagram, the "display" and "speaker" components are included to
+show what the complete system looks like. The scope of this project only
+includes the components inside the area marked "game console" and the gamepad
+components.
# Game controllers
@@ -60,7 +83,13 @@ The state machine will be designed with the following states:
# PPU
-Here's a list of features our PPU has:
+As mentioned in the [research document](research.md#graphics), the PPU designed
+for this project is heavily inspired by the NES's PPU. Because our game does
+need slightly different graphical capabilities, the differences between the NES
+PPU and our custom PPU are highlighted here. Readers of this section are
+expected to know basic operation of the NES's PPU.
+
+PPU features:
- 320x240 @ 60Hz VGA output (upscaled to 640x480)
- single tilemap with room for 1024 tiles of 16x16 pixels
@@ -71,8 +100,7 @@ Here's a list of features our PPU has:
- sprites are always drawn on top of the background layer
- PPU control using DMA (dual-port asynchronous RAM)
- tiles can be flipped using FAM or BAM
-- no frame buffer
-- vertical and horizontal sync and blank output
+- vertical and horizontal blank output
Notable differences:
@@ -80,60 +108,63 @@ Notable differences:
- NES OAM equivalent is called FAM (foreground attribute register)
- 320x240 @ 60Hz output
- Since we're using VGA, we can't use custom resolutions without an
- upscaler/downscaler. This resolution was chosen because it's exactly half of
- the lowest standard VGA resolution 640x480.
+ Since the FPGA board we're using has a VGA port, the PPU outputs VGA. VGA
+ does not support custom resolutions. This resolution was chosen because it's
+ exactly half of the lowest standard VGA resolution 640x480. This allows the
+ PPU to use nearest-neighbor upscaling, which will lead to a simpler hardware
+ implementation.
- No scanline sprite limit
- Unless not imposing any sprite limit makes the hardware implementation
- impossible, or much more difficult, this is a restriction that will likely
- lead to frustrating debugging sessions, so will not be replicated in our
- custom PPU.
+ This was a hardware limitation of the original NES, which our PPU design does
+ not have.
- Sprites are 16x16
Most NES games already tile multiple 8x8 tiles together into "metatiles" to
- create the illusion of larger sprites. This was likely done to save on memory
- costs as RAM was expensive in the '80s, but since we're running on an FPGA
- cost is irrelevant.
+ create the illusion of larger sprites. This however is wasteful of the
+ available foreground sprites, so this PPU has 16x16 pixel sprites by default.
- Single 1024 sprite tilemap shared between foreground and background sprites
The NES OAM registers contain a bit to select which tilemap to use (of two),
which effectively expands each tile's index address by one byte. Instead of
creating the illusion of two separate memory areas for tiles, having one
- large tilemap seems like a more sensible solution to indexed tiles.
+ large tilemap is a simpler solution.
- 8 total palettes, with 8 colors each
- More colors is better. Increasing the total palette count is a very memory
- intensive operation, while increasing the palette color count is likely slower
- when looking up color values for each pixel on real hardware.
+ More colors allows for nicer looking graphics. Increasing the palette color
+ count is a very memory intensive operation as this inflates the entire
+ tilemap, while increasing the total palette count increases FPGA utilization.
+ Keeping in mind that these palettes can be modified at any point during
+ runtime, an 8x8 palette table is likely big enough.
- Sprites can be positioned partially off-screen on all screen edges using only
the offset bits in the FAM register
The NES has a separate PPUMASK register to control special color effects, and
to shift sprites off the left and top screen edges, as the sprite offsets
- count from 0. Our PPU's FAM sprite offset bits count from -15, so the sprite
+ count from 0. Our PPU's FAM sprite offset bits count from -16, so the sprite
can shift past the top and left screen edges, as well as the standard bottom
and right edges.
-- No status line register, only V-sync and H-sync outputs are supplied back to
- CPU
+- No status line register, only V-blank and H-blank outputs are supplied back
+ to CPU
- The NES status line register contains some handy lines, such as a buggy
- status line for reaching the max sprite count per scanline, and a status line
- for detecting collisions between background and foreground sprites. Our PPU
- doesn't have a scanline limit, and all hitbox detection is done in software.
- Software hacks involving swapping tiles during a screen draw cycle can still
- be achieved by counting the V-sync and H-sync pulses using interrupts.
+ The NES status line register contains a buggy status line for reaching the
+ max sprite count per scanline, and a status line for detecting collisions
+ between background and foreground sprites. Our PPU doesn't have a scanline
+ limit, and all hitbox detection is done in software. Software hacks involving
+ swapping tiles during a screen draw cycle can still be achieved by counting
+ the V-blank and H-blank pulses using interrupts.
- No background scrolling splits
This feature allows only part of the background canvas to be scrolled, while
another portion stays still. This was used to draw HUD elements on the
background layer for displaying things like health bars or score counters.
- Since we are working with a higher foreground sprite limit, we'll use regular
+ Since this PPU has a higher foreground sprite limit, the game uses regular
foreground sprites to display HUD elements.
- Sprites are always drawn on top of the background layer
- Our game doesn't need this capability for any visual effects. Leaving this
- feature out will lead to a simpler hardware design
+ The NES PPU has the capability to draw 'foreground' sprites both behind and
+ in front of the background layer. Our game doesn't need this capability for
+ any visual effects. Leaving this feature out will lead to a simpler hardware
+ design.
- Sprites are positioned relative to the viewport, not the background layer
This leads to a simpler hardware architecture for the foreground sprite
@@ -149,20 +180,18 @@ Notable differences:
Important notes:
-- The STM32 can reset the PPU. This line will also be connected to a physical
- button on the FPGA.
- The STM32 uses direct memory access to control the PPU.
- The PPU's native resolution is 320x240. It works in this resolution as if it
is a valid VGA signal. The STM32 is also only aware of this resolution. This
resolution is referred to as "tiny" resolution. Because VGA-compatible LCD's
likely don't support this resolution due to low clock speed, a built-in
- pixel-perfect 2X upscaler is chained after the PPU's "tiny" output. This
+ pixel-perfect 2X upscaler is internally connected before the output. This
means that the display sees the resolution as 640x480, but the PPU and STM32
only work in 320x240.
-- The STM32 receives the TVSYNC and THSYNC lines from the PPU. These are the
- VSYNC and HSYNC lines from the tiny VGA signal generator. These lines can be
+- The STM32 receives the TVBLANK and THBLANK lines from the PPU. These are the
+ VBLANK and HBLANK lines from the "tiny" VGA resolution. These lines can be
used to trigger interrupts for counting frames, and to make sure no
- read/write conflicts occur for protected memory regions in the PPU.
+ simultanious reads and writes occur in the PPU.
- NVSYNC, NHSYNC and the RGB signals refer to the output of the native VGA
signal generator.
@@ -181,12 +210,12 @@ Important notes:
sprite with non-transparent color at current pixel in order, fallback to
background)
- (Palette lookup) lookup palette color using palette register
- - (VGA signal generator) output real color to VGA signal generator
+ - (Display controller) output upscaled tiny display signal
- The pipeline stages with two clock cycles contain an address set and memory
read step.
-- The pipeline takes 5 clock ticks in total. About 18 are available during each
- pixel. For optimal display compatibility, the output color signal should be
- stable before 50% of the pixel clock pulse width (9 clock ticks).
+- The pipeline takes 5 clock ticks in total. About 16 are available during each
+ pixel. Since each scanline is buffered in the upscaler, all available clock
+ cycles can be used (if necessary).
- Since the "sprite info" and "sprite render" steps are fundamentally different
for the foreground and background layer, these components will be combined
into one for each layer respectively. They are separated in the above diagram
@@ -197,6 +226,7 @@ Important notes:
the RAM in it's own cache memory. The cache updates are fetched during the
VBLANK time between each frame.
+
## Registers
diff --git a/docs/ppu.drawio b/docs/ppu.drawio
index c0ce0be..f7677be 100644
--- a/docs/ppu.drawio
+++ b/docs/ppu.drawio
@@ -1 +1 @@
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GMMZrTp06vmYaGSfomxOifyyfEX1aW/XvS1+8TsFxpwwct5Ny3BTEcVMMx7Um9jsNOsfx8VqDRVk94wTdFsBxDfFEaZIjZWKd5eBATizfTs41dPPBUy8Fns2kePLZmQXiaZQBT7S7s/G09xxPM76Vv0PvNb45AuCHCL/51sX86wah+75xKbZhhiP0DXV4UdBO08B2GrTFvn0bKmgXflyzUYz69mXcWKe0i2I0iEWJzKHTo09iaTaZ/fY4Cd3BfPjFrbfIjtxk8Uv0l8ns4cS9XzxAzap/X+vHT7W86A1Hrnfhv0zCiT+Lrt5Fa+4G0R8Waz2JbLoTbMDID0N/Gg0YepMHcEYr/kO4eOPQr259T+hUwQEngS0KOPRja8C1T/5HoBbdfohBEwb+s9v2PT9atM7Mny3E1v3E87BLaH2D5cMQyzudjMdfIg+iwiZZNjHAeKBzgeV9ExKkCAIINf8xHCs7SA+N09ebyz/9j6erP8+D2VnP+nVRMySQOPoWpX6NuA1gWTQtB+b256Oz9sdP99Z/fOqd/vwZ1O8/V3rS2qpcDL1oU3Sji57vP6P12FX4UAWBUJHEEj5U0qSSPdwghHWBpiDh432hxU321AlewNIoI07xq9cAIOKFkA5sD8ed3xVEdIgM6DXitYUji3eH7SHV0ybfM5DDn5MiAzOV3A7+7Z6pS1Q6FdhMFSM+SM2l1en0K1QY8gNSMPmBRMqPTuuqVYHEAEkXKuRJValgIf++qTFijggxMp/0OvCQLRKZrisayCLgSVr2KgQKFOYGqbAfVICIEdygoCXV0n530L1Sd3fNx4KC9hFuGGkNAo79DtFc3dut59r86qB9Z31qn2/9S8tb2fLMEA1SLXgnCtScTd1hFT7POVGghrtvGckw+HhTtzCKZQvjw3KCFNxJFbz8nLwOvlIJvbxODm9m87xz+Gt2rRv/G5jm0bjbvHTMGhlra43HgfsSoV0fu3f+2A2IVVI0wkRnTWYvbx4QwsJ19+hFukdO7Z+CFDNcBO2yDKD0RXHvsvin6FwQb76A90NiorZ7KisonC0a+PZy9nzkID9g1we0KnjqY27iRAd2xmsecZliLD06ExITFUqlyIOoVP16PSDdOqkgERMagzddUnYctk4rSMT4Q2BISJ/tQQWJqB0WhsQhILk6rSARqokaqpWqULMN111QsJKWe9Z3JnSALMmkOmiOzhmsRkugbwbGiDTsLyZz15vMFhl4d55/94wQ1OsP7swNhqFfbneNuc32kMddY1g7Uz3dI8tqbsFcJ7WWgaX2DrkiQuHWFowIqdoPzAoRMcYWfHvkJjkga59KjojQ2LNBOokGpDQvOSJCnZmGTiJC1u+WFRExEOTsT85BweEcj6JaWOWuvZDMC6CTAalSZgtJ4y8Db8/ZXYLk5w0gul8gi3DNcNRAbYNbRR5J3rY/nS9M7JKb/U5yPgtBD46Fk2UAnEq9JFJOUiDzjqFSiOQhXW4HPS5ZJEphJNQMdgDFqnwlkylA4/wiNd2L81dLvxz35hfz91/ebeOwlsWhn+5xUxsBgFcf3Ai4uTqd3ZeGvtS7L42Q57bIKOhhr14/Oi6b9u1sA6wgo8gife8RMFoFjGRmkQ29QE6rwomNk1AFxSbfp/9EH2vRf//dP6QW+4tQrIR68G0gga3XqDalBDgJjUY6uzeF46U04baQECXKJpXHxR6gvImavKNYIRKfZOdCg6pQKVZf0kGDo0JFcA0Q6a/hqQ6JQAJzl5tpXNWp3xmx+hAZY1joQ9U7U6j201CtBTk1QMKun4/XWXzyMqxL7tFJH8t3FB23oiXFC3zu1aExrGRz5PmTBa89KgXIEy9UksHEyxHdEj7+ZrxNxEqgrmQuo68EPgE7sSJzYwmYTnvU3GRHOlHV63U6wQuky0EnG2OTzmATNt5ink5iZpyQdx8UGA0ZkmssrNYgabfrXPqgQKtikX6Vq4nnTiOdU69P3akf/0YJml3TWSNFYQ0MIVCxr3SziaxAcbZkYJBInwynXqjFWJdZMUne9JMfRGQOlNrtanN6j8SCRCYTKt3tKCeMeEUFYIxKVgGQE0ZC89SApKTitWGRlefwqgA9RIZ3zw9fpFn8YBgGk9Hr10kwlXL8TSKJlWPS6iuhcpwCqCKUYyC4r75ynAITCZRjINJfQuU4/XskFiTSyCyfcpweI6HKsU1ameVTjtNjxEs5Bg801/cosLlVP1+PY4BPCUSd9yoqhhJECouKwdyR4UxNE+voZTRJw0qzoVfK5iX3yK3p0A/clWX1Mg8mC7MqizWV2G6CzS6B1hSdOemKecXCWLLdKytQRbh2oMNPVaq3zooJ+isW5haKkQ6UNHWv2kfVm8Q6o1YkSkDjsS17ObnROHlI/h06/QDrk8cxefD6kE6ByN6s8emEzbvcy8lk0ayoIj75HL4fUt9a+D0rbOTbrw047lxBVWiVAHx7u+eQ8Rb8ZlILj9vakJH5L4mzvx3fMXtyy45OJ0p6dVQMWGS5y5fM4QOW5DKnuF59cObA7iW/nIUMFMzIo48kbCKR8kThXkd0JkjCTKC1500FiUy6pLm795mz7DCK1k+Ag834dLuQKMfA3N0rJoaupJV63i2bRCnu6Er4ld+jsi5yiZMWcaGGl+vRT3A50LFiRUc/ke6VtCQQG4/e68Q1WaknoJQxvtFVGYq48OiqHmMhJiwHrwuxLBt5q1V09Zs5kkRXwZusoqupgCoiN0jxZtZZIREcXAVvl/RtbdkjMkbttq1KatsICmrmEbQDb5uMPC9idnzOeJbG8UfliSSKN1l78uU/r5CRbQsgddAv33kFVAKgeIXrYNstcf6GaIm/ap4pwh0Grw3cNaC2v2dmJwvX0YlSvJ8Mvj/SvvsSOXzAklvkpMBKDDZ5u9xzEzK8wnXwMpQqXEdngizMLFW4LiskRWiSGqnzqxz/yMnfw6teD749eXVIkSlf8LNs0SFVT/miE0VSHRLxtmQpX1mxEoINSqRXJuZKbfPAjrnGVC065mqitiSrjYcRdCUmGAJioijVX23yoAZ6TPLospAHO0eXGbHHJ6DeoHzJY5SVPNS86L0nj2UIqHU3ZGoo/o+VB32u7u3Wc21+ddC+sz61z7f+peXVNCchfZDHpWj62FjnA81mtXwuolWCoVqmGUyeRkLy2JJsXDZ+ELXDIg82QRdCnmYZyAMdNUGL6hfNHRNLO9SZ+xY+oSlA6UGOE2W4Q/XIMwUPqrQpnDy4HGGmoGITTFOA4DFVs9WpsQM2eSTpDmUaGHkcFnmwCaYlgjyqmVuwytNMSB7k9yqaPDae/N5gqTz4CSZNEeSRydzi5yUEKjOobcYLJw9eDsA0tvDubLYI8qhmbFHbPbPJI4vkwXWeZkpjyxAieVQztqg9jtnkMSQhj5EyPoFPwNyKfMhjqWZtUQUKW+eR1M1jpJU8lhDyqGZtUQUKmzySSh5mfAKfYGkiyKOXgTxIoDB9hJJUMuMuPyutj9CoC/ARWqpZ6lR5wuROUxLu4GeTaizuYBMMTQR3TMW489ZtGZ2jN6t/cvl0PLj+7I6Of68yGde5A7uDcg+qZ0q2Qn4DtdFB+y2zvb9k4Kjm46KtOdvQlETsOng5NyskjE/QRXgpLNW8FPCLndTQtCVxcTlOSuc6PsEQYWjaqhmaMHmSHvqiS5IIR0geM6XkcURwRzV9D6REYjuTj48CaHGFBeHwQySXNxrP+uZAeqMDO3iPFd/Bx2MHFXHioGpnVsEcTJoPJYyDmF+rIYiDLAWsGA6WQnmHLKtiOYg55mP9ijsHWXpcMRxULc4Nq2eA76VYDmIJ5E1BHGQFrYrhoGqGKMxBILG9e9rseObL8enTaDq6vj1rNW+bq3Qw7iTEG3NqdU4sJLrbMTN+NsYbcY4TVxIibVgZEsIGbWISShI5dfR0xgQ+frPLLjG+kWW0kKofRzVHC23fZQf05WAlY5tkTxCSSeToilEHFGkmYF9QM2WLJg9nkUbky6Ydr4vIr3VUiyomTlQCt1tZaoqyJyo1WZIw23ghNUuOas7BxCmYMDklEZx4FQk7BRObYNcZZLOyjTdFdBFwVPMaZoy8ycFNTAwy425FZJY7qJdakaeBNPDaMeCkK6jRFx6t2iWFBs7LIju8H8/mr0u0BZz/keNJH/BRIjud/7HiSqrzP4QCB5yg2u8OuuqcUZYVmPdNUFbeNxKjPDq1wRglPlwi49OnFkS4jxFYlTzOlKCmgm4eKqEMb+lMEN9DkJrwiTXjrEAQ09+XmquH9dysMBFzKMTwpTfwai9vp0fnH7efrU794Oi8ZpBdsYUrjTpu+FmkzggdCqTVea0KcBzEbGle6PVfvdZieSJCDRff8+DO3GAYRiwUo0/ilF6pi6kVzaX6mPo8OTqNUumTgkHVCVCVPk8uK1CctwgYo92Pj0j3uKn7i0O2Tx4aJLwMgO1TMqIWeHwEfD/kRtmrIJFKdpDG6EGFkEzKpkb64oqW7nDqB8RbfsKePPZEHTuVzgNZZDvpsOEh2/cTgSJEOXDMDA9RvteACJXcOqmQyim5eZ3yBq8KqRP+GtyctdWm6ooLkkhvndT7jioUCpbghrSGPBQK4ichSN1O4XMg6UyQRVyQyt5NBUlBssNoXM6H/bl78scOnfPLcdvqv9dUyx0Fs+6ASg2qK1B8RxoQG9VSJ0FsgHJCqk9QEmxUyxyEK5eAegCqO1AScFQrxIXBAXKOwdXQpcJGtQJVGBs9ITa5p4Nnwga972qDA7RAo9oTsoCjWltQEBzgvDuqZSELOKr1YUpcH0hN/+Bed+8Qp35tfkVeZfdS107nXGQIE1w1Q5EaHlwnOPwmyFFkaNCpwB6fc9k9TB3VbCVqXJNNHTkODzLwVpeMvl7E+Jz7qsLUUc2So0Zg2dSRozWmgRd8MNpx4ePzrtCDqaOaoUmNirKpw6cTUmrq4GW+jKJ4YrwugDq6amYwNZTLpI4kR4sbePsCxgEMxPicK8rhChQyFHv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En0VX76I1d4PoD4u1nkQ23Qk2YOSHoT+NBgy9yQM4oxX/IVy8cehXt74ndKrggJPAFgUc+rE14Non/yNQi24/xKAJA//ZbfueHy1aZ+bPFmLrfuJ52CW0vsHyYYjlnU7G4y+RB1FhkyybGGA80LnA8r4JCVIEAYSa/xiOlR2kh8bp683ln/7H09Wf58HsrGf9uqgZEkgcfYtSv0bcBrAsmpYDc/vz0Vn746d76z8+9U5//gzq958rPWltVS6GXrQputFFz/ef0XrsKnyogkCoSGIJHyppUskebhDCukBTkPDxvtDiJnvqBC9gaZQRJ+RHBSDihZAObA/Hnd8VRHSIDOg14rWFI4t3h+0h1dMm3zPiVXA4KTIwU8nt4N/umbpEpVOBzVQx4oPUXFqdTr9ChSE/IAWTH0ik/Oi0rloVSAyQdKFCnlSVChby75saI+aIECPzSa8DD9kikem6ooEsAp6kZa9CoEBhbpAK+0EFiBjBDQpaUi3tdwfdK3V313wsKGgf4YaR1iDg2O8QzdW93Xquza8O2nfWp/b51r+0vJUtzwzRINWCd6JAzdnUHVbh85wTBWq4+5aRDIOPN3ULo1i2MD4sJ0jBnVTBy8/J6+ArldDL6+TwZjbPO4e/Zte68b+BaR6Nu81Lx6yRsbbWeBy4LxHa9bF754/dgFglRSNMdNZk9vLmASEsXHePXqR75NT+KUgxw0XQLssASl8U9y6Lf4rOBfHmC3g/JCZqu6eygsLZooFvL2fPRw7yA3Z9QKuCpz7mJk50YGe85hGXKcbSozMhMVGhVIo8iErVr9cD0q2TChIxoTF40yVlx2HrtIJEjD8EhoT02R5UkIjaYWFIHAKSq9MKEqGaqKFaqQo123DdBQUrablnfWdCB8iSTKqD5uicwWq0BPpmYIxIw/5iMne9yWyRgXfn+XfPCEG9/uDO3GAY+uV215jbbA953DWGtTPV0z2yrOYWzHVSaxlYau+QKyIUbm3BiJCq/cCsEBFjbMG3R26SA7L2qeSICI09G6STaEBK85IjItSZaegkImT9blkREQNBzv7kHBQczvEoqoVV7toLybwAOhmQKmW2kDT+MvD2nN0lSH7eAKL7BbII1wxHDdQ2uFXkkeRt+9P5wsQuudnvJOezEPTgWDhZBsCp1Esi5SQFMu8YKoVIHtLldtDjkkWiFEZCzWAHUKzKVzKZAjTOL1LTvTh/tfTLcW9+MX//5d02DmtZHPrpHje1EQB49cGNgJur09l9aehLvfvSCHlui4yCHvbq9aPjsmnfzjbACjKKLNL3HgGjVcBIZhbZ0AvktCqc2DgJVVBs8n36T/SxFv373/1DarG/CMVKqAffBhLYeo1qU0qAk9BopLN7UzheShNuCwlRomxSeVzsAcqbqMk7ihUi8Ul2LjSoCpVi9SUdNDgqVATXAJH+Gp7qkAgkMHe5mcZVnfqdEasPkTGGhT5UvTOFaj8N1VqQUwMk7Pr5eJ3FJy/DuuQenfSxfEfRcStaUrzA514dGsNKNkeeP1nw2qNSgDzxQiUZTLwc0S3h42/G20SsBOpK5jL6SuATsBMrMjeWgOm0R81NdqQTVb1epxO8QLocdLIxNukMNmHjLebpJGbGCXn3QYHRkCG5xsJqDZJ2u86lDwq0KhbpV7maeO400jn1+tSd+vFvlKDZNZ01UhTWwBACFftKN5vIChRnSwYGifTJcOqFWox1mRWT5E0/+UFE5kCp3a42p/dILEhkMqHS3Y5ywohXVADGqGQVADlhJDRPDUhKKl4bFll5Dq8K0ENkePf88EWaxQ+GYTAZvX6dBFMpx98kklg5Jq2+EirHKYAqQjkGgvvqK8cpMJFAOQYi/SVUjtO/R2JBIo3M8inH6TESqhzbpJVZPuU4PUa8lGPwQHN9jwKbW/Xz9TgG+JRA1HmvomIoQaSwqBjMHRnO1DSxjl5GkzSsNBt6pWxeco/cmg79wF1ZVi/zYLIwq7JYU4ntJtjsEmhN0ZmTrphXLIwl272yAlWEawc6/FSleuusmKC/YmFuoRjpQElT96p9VL1JrDNqRaIENB7bspeTG42Th+TfodMPsD55HJMHrw/pFIjszRqfTti8y72cTBbNiirik8/h+yH1rYXfs8JGvv3agOPOFVSFVgnAt7d7DhlvwW8mtfC4rQ0Zmf+SOPvb8R2zJ7fs6HSipFdHxYBFlrt8yRw+YEkuc4rr1QdnDuxe8stZyEDBjDz6SMImEilPFO51RGeCJMwEWnveVJDIpEuau3ufOcsOo2j9BDjYjE+3C4lyDMzdvWJi6EpaqefdskmU4o6uhF/5PSrrIpc4aREXani5Hv0ElwMdK1Z09BPpXklLArHx6L1OXJOVegJKGeMbXZWhiAuPruoxFmLCcvC6EMuykbdaRVe/mSNJdBW8ySq6mgqoInKDFG9mnRUSwcFV8HZJ39aWPSJj1G7bqqS2jaCgZh5BO/C2ycjzImbH54xnaRx/VJ5IoniTtSdf/vMKGdm2AFIH/fKdV0AlAIpXuA623RLnb4iW+KvmmSLcYfDawF0Davt7ZnaycB2dKMX7yeD7I+27L5HDByy5RU4KrMRgk7fLPTchwytcBy9DqcJ1dCbIwsxSheuyQlKEJqmROr/K8Y+c/D286vXg25NXhxSZ8gU/yxYdUvWULzpRJNUhEW9LlvKVFSsh2KBEemVirtQ2D+yYa0zVomOuJmpLstp4GEFXYoIhICaKUv3VJg9qoMckjy4LebBzdJkRe3wC6g3KlzxGWclDzYvee/JYhoBad0OmhuL/WHnQ5+rebj3X5lcH7TvrU/t8619aXk1zEtIHeVyKpo+NdT7QbFbL5yJaJRiqZZrB5GkkJI8tycZl4wdROyzyYBN0IeRploE80FETtKh+0dwxsbRDnblv4ROaApQe5DhRhjtUjzxT8KBKm8LJg8sRZgoqNsE0BQgeUzVbnRo7YJNHku5QpoGRx2GRB5tgWiLIo5q5Bas8zYTkQX6voslj48nvDZbKg59g0hRBHpnMLX5eQqAyg9pmvHDy4OUATGML785miyCPasYWtd0zmzyySB5c52mmNLYMIZJHNWOL2uOYTR5DEvIYKeMT+ATMrciHPJZq1hZVoLB1HkndPEZayWMJIY9q1hZVoLDJI6nkYcYn8AmWJoI8ehnIgwQK00coSSUz7vKz0voIjboAH6GlmqVOlSdM7jQl4Q5+NqnG4g42wdBEcMdUjDtv3ZbROXqz+ieXT8eD68/u6Pj3KpNxnTuwOyj3oHqmZCvkN1AbHbTfMtv7SwaOaj4u2pqzDU1JxK6Dl3OzQsL4BF2El8JSzUsBv9hJDU1bEheX46R0ruMTDBGGpq2aoQmTJ+mhL7okiXCE5DFTSh5HBHdU0/dASiS2M/n4KIAWV1gQDj9Ecnmj8axvDqQ3OrCD91jxHXw8dlARJw6qdmYVzMGk+VDCOIj5tRqCOMhSwIrhYCmUd8iyKpaDmGM+1q+4c5ClxxXDQdXi3LB6BvheiuUglkDeFMRBVtCqGA6qZojCHAQS27unzY5nvhyfPo2mo+vbs1bztrlKB+NOQrwxp1bnxEKiux0z42djvBHnOHElIdKGlSEhbNAmJqEkkVNHT2dM4OM3u+wS4xtZRgup+nFUc7TQ9l12QF8OVjK2SfYEIZlEjq4YdUCRZgL2BTVTtmjycBZpRL5s2vG6iPxaR7WoYuJEJXC7laWmKHuiUpMlCbONF1Kz5KjmHEycggmTUxLBiVeRsFMwsQl2nUE2K9t4U0QXAUc1r2HGyJsc3MTEIDPuVkRmuYN6qRV5GkgDrx0DTrqCGn3h0apdUmjgvCyyw/vxbP66RFvA+R85nvQBHyWy0/kfK66kOv9DKHDACar97qCrzhllWYF53wRl5X0jMcqjUxuMUeLDJTI+fWpBhPsYgVXJ40wJairo5qESyvCWzgTxPQSpCZ9YM84KBDH9fam5eljPzQoTMYdCDF96A6/28nZ6dP5x+9nq1A+OzmsG2RVbuNKo44afReqM0KFAWp3XqgDHQcyW5oVe/9VrLZYnItRw8T0P7swNhmHEQjH6JE7plbqYWtFcqo+pz5Oj0yiVPikYVJ0AVenz5LICxXmLgDHa/fiIdI+bur84ZPvkoUHCywDYPiUjaoHHR8D3Q26UvQoSqWQHaYweVAjJpGxqpC+uaOkOp35AvOUn7MljT9SxU+k8kEW2kw4bHrJ9PxEoQpQDx8zwEOV7DYhQya2TCqmckpvXKW/wqpA64a/BzVlbbaquuCCJ9NZJve+oQqFgCW5Ia8hDoSB+EoLU7RQ+B5LOBFnEBans3VSQFCQ7jMblfNifuyd/7NA5vxy3rf57TbXcUTDrDqjUoLoCxXekAbFRLXUSxAYoJ6T6BCXBRrXMQbhyCagHoLoDJQFHtUJcGBwg5xhcDV0qbFQrUIWx0RNik3s6eCZs0PuuNjhACzSqPSELOKq1BQXBAc67o1oWsoCjWh+mxPWB1PQP7nX3DnHq1+ZX5FV2L3XtdM5FhjDBVTMUqeHBdYLDb4IcRYYGnQrs8TmX3cPUUc1WosY12dSR4/AgA291yejrRYzPua8qTB3VLDlqBJZNHTlaYxp4wQejHRc+Pu8KPZg6qhma1Kgomzp8OiGlpg5e5ssoiifG6wKoo6tmBlNDuUzqSHK0uIG3L2AcwECMz7miHK5AIUOx569hmUpgt1WqbE0qwVunrRQNRjGsxq2m0Nw9np5bnQ6xKlD9Br8VKFVOPJ0EkhRZmqXKic8KSREll2apcuJzQohXZiWsyejyCXYTWoE8cqSoZsDaCpzxSqOUmagrJkgi3ZGOvY4Lr8RKRXApIluKLFUuXn7wysKm5RKsLcCV4uKDygPx0oOWRbCOiuLCIyMqnGVH7y447wzvz42b62nfNkbO8G9DStnhcJId4AJAsuPgpHWmcFsAKhHECw/wdiDhUcFSoPToz0dn7Y+f7q3/+NQ7/fkzqN9/AiiFk9niZiRrkbJ0Eubohczd36gl8DeCzVLy8LZRDwgoS7OU7JDBzWyywwO3mJNg58ZXYLWT5+0OhglauYNTkDZvUsKQVO7gFJBw3rFhhCp3cHqEhLqDkRwvVLDjqZ+82qHQCuOU7IZCh1wSMa5yM5SsABQitFVuhpITIGJltAS5GLiMBs2PPNxmtHIlzl0NZGJkcZkXtJIkzj0M9hOAIvIsMvRH4qe28YrCUUt/le2FRMddErkA9DhWqxdSVhSKiLLJKBuERtmANmm8ojnFsJIKuyQxNaBLWgVCwZJhj6oQlxz4N45HLb9nHP+GDeIBFH3QpMN6zQctVi++uh68mz2qAuQHHVCuQ4vnc4cu+hj4frhePxMJl8dTf+wuRvwf
\ No newline at end of file
--
cgit v1.2.3
From f53db3c725838e89a6148b2c629093862d57519c Mon Sep 17 00:00:00 2001
From: UnavailableDev <69792062+UnavailableDev@users.noreply.github.com>
Date: Wed, 15 Mar 2023 22:19:50 +0100
Subject: Update architecture.md
---
docs/architecture.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index 9be6751..36bec75 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -401,7 +401,7 @@ optional:
- envelope (ADSR)
-
+
This image shows an advanced method of generating tones. In our case this is only an indication as to how it could be done, we will actually only be looking at the sustained tone part for simplicity sakes.
In order to get the correct graph forms, some data points can be stored in a LUT (Look Up Table). This allows the saving of computation power at the cost of some ROM space.
--
cgit v1.2.3
From 51ee4672d5f2f734eb40f4312a2aefd2f8c6dc03 Mon Sep 17 00:00:00 2001
From: BjornMartens <113104306+BjornMartens@users.noreply.github.com>
Date: Thu, 16 Mar 2023 09:58:34 +0100
Subject: Added top level stm
---
docs/architecture.md | 11 +++++++++++
1 file changed, 11 insertions(+)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index cf4440f..3b4a877 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -31,6 +31,17 @@ To ensure a smooth and enjoyable gaming experience, it is essential to address a
## STM32
### game engine
+The game engine is designed to run a 2D platformer game. The game engine has to manage all the different game states. To do this it will utilize a finite state machine (FSM). The game engine will also cover de input handling from the player, the game logic for example enemy handling or the powerup handling it will also send out data to the APU (Audio processing unit) so that the right sounds will be played.
+
+FSM is a useful tool for managing game states and transitions. The game has many different states such as: title screen, shop and gameplay state. Each state represents a particular configuration from the with different logic and variables.
+
+The state machine is designed to have the following states:
+1. Initialization: The initialization state will be responsible for initializing all game-related variables and subsystems, including the FPGA-based picture processing unit.
+2. Title Screen: The title screen state will display the game's title screen and wait for user input to start the game or access the options menu.
+3. Options: The options state will allow the user to configure game settings, such as sound and graphics options.
+4. Game Play: The game play state will be responsible for running the game logic and updating the game state.
+5. Game Over: The game over state will display the game over screen and wait for user input to restart the game or return to the title screen.
+
### user input
### PPU communication
### APU communication
--
cgit v1.2.3
From edee448b453c683ca968a8dacaa37508ec649c8c Mon Sep 17 00:00:00 2001
From: Flenk008
Date: Thu, 16 Mar 2023 12:46:18 +0100
Subject: Update architecture.md
Added SPI (STM32, BASYS3)
---
docs/architecture.md | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index 36bec75..bea35be 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -430,3 +430,23 @@ To index tiles from the tilemap, 10 bits will be used for both the foreground
and background layers of the PPU. This means that the global tilemap can fit up
to 1024 tiles in total, each being 16x16 pixels (the example uses 4x4 tiles for
illustration purposes).
+
+
+### PPU communication
+
+To comunicate with the FPGA via the STM32 a protocol is needed. After [research](research.md#Input) of different possible protocols, SPI was the best option for this problem. As there is only one master and one slave, four data lines are needed at maximum. The STM32 will be the master and the FPGA will be the slave. The STM32 has a configurable SPI module that is easily configurable unlike the FPGA. Futhermore, the MISO line is not needed because the FPGA does not send any big data to the STM32. The slave select line will operate as a write enable.
+
+
+
+### SPI
+
+The FPGA will configure as a slave of the SPI protocol. THe FPGA (Basys3) does not have a IP-Core that supports external SPI communication so the SPI slave has to be designed. The module requires three inputs as mentioned before in the [STM32](architecture.md#STM32) section.
+
+
+### PPU communication
+
+The SPI module will be configured that sends 8 bits per cycle and at a speed of 1.0 MB/s. The STM32 Cube IDE SPI module does not include a slave select line so a pin has to configured manually to fullfill this purpose. Every data transfer consists out of 4 times 8 bits, so 32 bits in total. The first byte is the address and the other 3 bytes consist the data.
+
+
+### SPI
+The FPGA uses 3 JMOD pins to receive the SPI data. The FPGA does not have a IP-Core for SPI. To receive the data the module has 3 synchronisers for the incoming SPI clock, data and slave select. The data will be read via the SPI protocol and shifted untill all 32 bits are read.
--
cgit v1.2.3
From 3b9864c7e6382acc0a6727920ef0f92c33af250d Mon Sep 17 00:00:00 2001
From: lonkaars
Date: Thu, 16 Mar 2023 13:06:27 +0100
Subject: merge niels docs
---
assets/TopLevel.PNG | Bin 0 -> 13919 bytes
assets/hh_introScreen.png | Bin 0 -> 130932 bytes
docs/BobSprint2.md | 19 +++++++++++++++++++
docs/architecture.md | 38 +++++++++++++++++++++++++++++++++-----
4 files changed, 52 insertions(+), 5 deletions(-)
create mode 100644 assets/TopLevel.PNG
create mode 100644 assets/hh_introScreen.png
create mode 100644 docs/BobSprint2.md
(limited to 'docs')
diff --git a/assets/TopLevel.PNG b/assets/TopLevel.PNG
new file mode 100644
index 0000000..2a7b16d
Binary files /dev/null and b/assets/TopLevel.PNG differ
diff --git a/assets/hh_introScreen.png b/assets/hh_introScreen.png
new file mode 100644
index 0000000..8b6e192
Binary files /dev/null and b/assets/hh_introScreen.png differ
diff --git a/docs/BobSprint2.md b/docs/BobSprint2.md
new file mode 100644
index 0000000..6fff8fc
--- /dev/null
+++ b/docs/BobSprint2.md
@@ -0,0 +1,19 @@
+
+
+# Proud of
+Simulation: We're proud of the simulation that we created to test our game because it allows us to identify and address potential issues before the game is released. This helps ensure that the game is as polished and bug-free as possible.
+
+PPU: Our use of an FPGA-based PPU (Picture Processing Unit) in our game engine allows us to achieve high-quality graphics and smooth animation. This is important because it helps create an immersive and engaging gaming experience.
+
+Upscaling: We've implemented a sophisticated upscaling that allows us to scale up our game. This Ensures that our game runs smoothly and without any
+
+Collisions: We've put a lot of effort into making sure that our collision detection system is accurate and reliable. This ensures that the game mechanics work as intended and that players are able to navigate the game world without frustration.
+
+Artwork: We're proud of the artwork that was created which is stunning and imaginative artwork that brings the game world to life. From character designs to background artwork, every aspect of the game has been given careful attention to ensure that it looks as good as it plays. And more is coming!
+# Challegens
+Upscaling: While our upscaling algorithm is sophisticated, one of the challenges we faced was synchronization. Because we're upscaling in real-time, we had to ensure that the upscaling process didn't cause any lag or delay in the game. This required careful optimization of the algorithm and synchronization with other game components.
+
+PPU: While the use of an FPGA-based PPU allowed us to achieve high-quality graphics, it also presented some challenges. Specifically, the limited resources of the FPGA required us to optimize the PPU code to ensure that it could handle the demands of real-time gameplay.
+
+Communication bug fixes on the STM32: As with any complex system, we encountered some bugs in the communication between the STM32 microcontroller and the other components of the system. This required careful debugging and troubleshooting to identify and fix the issues.
+
diff --git a/docs/architecture.md b/docs/architecture.md
index 36bec75..c2eb655 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -1,18 +1,46 @@
-# General system architecture
+# Hooded Havic: Miniboss Mania
+
+
+
+# introduction
+Welcome to Hooded Havoc: Miniboss Mania, an exciting 2D platformer game created by our team Joshua, Loek, Bjorn, Frenk and Niels! This game was developed using the STM32 microcontroller as the game engine and the FPGA as the Picture Processing Unit (PPU).
+
+In Hooded Havoc: Miniboss Mania, you will take on the role of a brave hero who must battle through multiple levels filled with challenging obstacles and formidable minibosses. With smooth gameplay and engaging graphics, you will feel immersed in a world of adventure and excitement.
+
+Our use of the STM32 microcontroller and FPGA PPU allowed us to create a unique and innovative gaming experience. The STM32 provides efficient and reliable processing power, while the FPGA ensures that our graphics are rendered smoothly and accurately.
+
+So get ready to embark on a thrilling journey through Hooded Havoc: Miniboss Mania, and see how far you can make it!
+## Objective
+The objective of Hooded Havoc: Miniboss Mania is to guide the hero through multiple levels, defeating minibosses and overcoming obstacles along the way. The ultimate goal is to reach the final boss and defeat them to retrieve the stolen staff.
+
+To achieve this objective, the player must use their platforming skills to jump, run, and dodge obstacles while also battling enemies and minibosses. Each level presents a unique challenge that will require the player to adapt and strategize to overcome.
+
+As the player progresses through the game, they will unlock new abilities and power-ups that will aid them in their journey. The player must use these abilities wisely to defeat the minibosses and ultimately save the world.
+
+So, the objective of Hooded Havoc: Miniboss Mania is not only to provide an exciting and engaging gaming experience but also to challenge players to use their skills and strategic thinking to overcome obstacles and emerge victorious.
+## Problem statement
+One potential problem that could arise in the development of Hooded Havoc: Miniboss Mania is related to the PPU and communication between the STM32 and PPU.
+
+The PPU is responsible for rendering the graphics and displaying them on the screen, while the STM32 is responsible for processing the game logic and input from the player. However, if there is a problem with the communication between these two components, it could lead to synchronization issues and graphical glitches that could affect the player's experience.
The existing hardware components available for building this project consists
of:
+For example, if the PPU is unable to keep up with the processing speed of the STM32, the graphics may lag or appear distorted, causing the game to become unplayable. Similarly, if there is a delay in communication between the STM32 and PPU, it could result in a mismatch between the game logic and the displayed graphics, leading to confusion for the player.
-- Raspberry Pi
-- Nucleo STM32 development board
-- Basys3 FPGA development board
-- Arduino Uno R3
+To ensure a smooth and enjoyable gaming experience, it is essential to address any potential issues with the PPU and communication between the STM32 and PPU during the development process. This may involve optimizing the code for both components, adjusting the communication protocol, or adding buffer systems to prevent lag or synchronization issues.
+
+# General system architecture
The Raspberry Pi is by far the most powerful component out of these 4, but
because one of the project requirements is that no general-purpose operating
system is used, utilizing the Raspberry Pi will involve writing low-level
drivers for its interfaces, which will likely cost a lot of effort.
+- Raspberry Pi
+- Nucleo STM32 development board
+- Basys3 FPGA development board
+- Arduino Uno R3
+
As to not risk project failure due to hardware constraints, the decision was
made to use the STM32 microcontroller and FPGA in combination, as these two are
both familiar and still relatively powerful platforms. Because audio and video
--
cgit v1.2.3
From 0fb8c4c52d185244898bac5745df6730a5c6ed5e Mon Sep 17 00:00:00 2001
From: lonkaars
Date: Thu, 16 Mar 2023 17:58:20 +0100
Subject: restructure architecture document
---
docs/architecture.md | 78 +++++++++++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 38 deletions(-)
(limited to 'docs')
diff --git a/docs/architecture.md b/docs/architecture.md
index c880b5d..831e6e4 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -1,8 +1,9 @@
-# Hooded Havic: Miniboss Mania
+
-# introduction
+# Introduction
+
Welcome to Hooded Havoc: Miniboss Mania, an exciting 2D platformer game created by our team Joshua, Loek, Bjorn, Frenk and Niels! This game was developed using the STM32 microcontroller as the game engine and the FPGA as the Picture Processing Unit (PPU).
In Hooded Havoc: Miniboss Mania, you will take on the role of a brave hero who must battle through multiple levels filled with challenging obstacles and formidable minibosses. With smooth gameplay and engaging graphics, you will feel immersed in a world of adventure and excitement.
@@ -10,7 +11,9 @@ In Hooded Havoc: Miniboss Mania, you will take on the role of a brave hero who m
Our use of the STM32 microcontroller and FPGA PPU allowed us to create a unique and innovative gaming experience. The STM32 provides efficient and reliable processing power, while the FPGA ensures that our graphics are rendered smoothly and accurately.
So get ready to embark on a thrilling journey through Hooded Havoc: Miniboss Mania, and see how far you can make it!
+
## Objective
+
The objective of Hooded Havoc: Miniboss Mania is to guide the hero through multiple levels, defeating minibosses and overcoming obstacles along the way. The ultimate goal is to reach the final boss and defeat them to retrieve the stolen staff.
To achieve this objective, the player must use their platforming skills to jump, run, and dodge obstacles while also battling enemies and minibosses. Each level presents a unique challenge that will require the player to adapt and strategize to overcome.
@@ -18,29 +21,32 @@ To achieve this objective, the player must use their platforming skills to jump,
As the player progresses through the game, they will unlock new abilities and power-ups that will aid them in their journey. The player must use these abilities wisely to defeat the minibosses and ultimately save the world.
So, the objective of Hooded Havoc: Miniboss Mania is not only to provide an exciting and engaging gaming experience but also to challenge players to use their skills and strategic thinking to overcome obstacles and emerge victorious.
+
## Problem statement
+
One potential problem that could arise in the development of Hooded Havoc: Miniboss Mania is related to the PPU and communication between the STM32 and PPU.
The PPU is responsible for rendering the graphics and displaying them on the screen, while the STM32 is responsible for processing the game logic and input from the player. However, if there is a problem with the communication between these two components, it could lead to synchronization issues and graphical glitches that could affect the player's experience.
-The existing hardware components available for building this project consists
-of:
For example, if the PPU is unable to keep up with the processing speed of the STM32, the graphics may lag or appear distorted, causing the game to become unplayable. Similarly, if there is a delay in communication between the STM32 and PPU, it could result in a mismatch between the game logic and the displayed graphics, leading to confusion for the player.
To ensure a smooth and enjoyable gaming experience, it is essential to address any potential issues with the PPU and communication between the STM32 and PPU during the development process. This may involve optimizing the code for both components, adjusting the communication protocol, or adding buffer systems to prevent lag or synchronization issues.
# General system architecture
-The Raspberry Pi is by far the most powerful component out of these 4, but
-because one of the project requirements is that no general-purpose operating
-system is used, utilizing the Raspberry Pi will involve writing low-level
-drivers for its interfaces, which will likely cost a lot of effort.
+The existing hardware components available for building this project consists
+of:
- Raspberry Pi
- Nucleo STM32 development board
- Basys3 FPGA development board
- Arduino Uno R3
+The Raspberry Pi is by far the most powerful component out of these 4, but
+because one of the project requirements is that no general-purpose operating
+system is used, utilizing the Raspberry Pi will involve writing low-level
+drivers for its interfaces, which will likely cost a lot of effort.
+
As to not risk project failure due to hardware constraints, the decision was
made to use the STM32 microcontroller and FPGA in combination, as these two are
both familiar and still relatively powerful platforms. Because audio and video
@@ -59,7 +65,19 @@ show what the complete system looks like. The scope of this project only
includes the components inside the area marked "game console" and the gamepad
components.
-# Game controllers
+# STM32 software
+
+The game engine will be designed to support 2D games. The engine will use a state machine to manage game states and transitions between them. The state machine will be implemented using a finite state machine (FSM) design pattern. The engine will also include support for handling user input, game logic, and sound.
+
+FSM is a useful tool for managing game states and transitions. A game can have many different states, such as a title screen, a level selection screen, a loading screen, and various gameplay states. Each state represents a particular configuration of the game, with different sets of variables, objects, and logic
+
+The state machine will be designed with the following states:
+
+1. Initialization: The initialization state will be responsible for initializing all game-related variables and subsystems, including the FPGA-based picture processing unit.
+2. Title Screen: The title screen state will display the game's title screen and wait for user input to start the game or access the options menu.
+3. Options: The options state will allow the user to configure game settings, such as sound and graphics options.
+4. Game Play: The game play state will be responsible for running the game logic and updating the game state.
+5. Game Over: The game over state will display the game over screen and wait for user input to restart the game or return to the title screen.
## Input
@@ -95,19 +113,13 @@ The buttons will be connected as follows:
To implement the input in the game, the input should be checked at the start of each game cycle. In this case there are no interrupts needed.
-# STM32 software
+## PPU communication
-The game engine will be designed to support 2D games. The engine will use a state machine to manage game states and transitions between them. The state machine will be implemented using a finite state machine (FSM) design pattern. The engine will also include support for handling user input, game logic, and sound.
-
-FSM is a useful tool for managing game states and transitions. A game can have many different states, such as a title screen, a level selection screen, a loading screen, and various gameplay states. Each state represents a particular configuration of the game, with different sets of variables, objects, and logic
+The SPI module will be configured that sends 8 bits per cycle and at a speed of 1.0 MB/s. The STM32 Cube IDE SPI module does not include a slave select line so a pin has to configured manually to fullfill this purpose. Every data transfer consists out of 4 times 8 bits, so 32 bits in total. The first byte is the address and the other 3 bytes consist the data.
-The state machine will be designed with the following states:
+## SPI
-1. Initialization: The initialization state will be responsible for initializing all game-related variables and subsystems, including the FPGA-based picture processing unit.
-2. Title Screen: The title screen state will display the game's title screen and wait for user input to start the game or access the options menu.
-3. Options: The options state will allow the user to configure game settings, such as sound and graphics options.
-4. Game Play: The game play state will be responsible for running the game logic and updating the game state.
-5. Game Over: The game over state will display the game over screen and wait for user input to restart the game or return to the title screen.
+The FPGA uses 3 JMOD pins to receive the SPI data. The FPGA does not have a IP-Core for SPI. To receive the data the module has 3 synchronisers for the incoming SPI clock, data and slave select. The data will be read via the SPI protocol and shifted untill all 32 bits are read.
# PPU
@@ -403,6 +415,15 @@ Format:
[custompputimings]: https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
+## PPU communication
+
+To comunicate with the FPGA via the STM32 a protocol is needed. After [research](research.md#Input) of different possible protocols, SPI was the best option for this problem. As there is only one master and one slave, four data lines are needed at maximum. The STM32 will be the master and the FPGA will be the slave. The STM32 has a configurable SPI module that is easily configurable unlike the FPGA. Futhermore, the MISO line is not needed because the FPGA does not send any big data to the STM32. The slave select line will operate as a write enable.
+
+## SPI
+
+The FPGA will configure as a slave of the SPI protocol. The FPGA (Basys3) does not have a IP-Core that supports external SPI communication so the SPI slave has to be designed. The module requires three inputs as mentioned before in the [STM32](architecture.md#STM32) section.
+
+
# APU
The Audio Processing Unit (APU) is programmed on the FPGA, here it will produce different signals on the audio output. These signals come in a few forms, as listed below.
@@ -459,22 +480,3 @@ and background layers of the PPU. This means that the global tilemap can fit up
to 1024 tiles in total, each being 16x16 pixels (the example uses 4x4 tiles for
illustration purposes).
-
-### PPU communication
-
-To comunicate with the FPGA via the STM32 a protocol is needed. After [research](research.md#Input) of different possible protocols, SPI was the best option for this problem. As there is only one master and one slave, four data lines are needed at maximum. The STM32 will be the master and the FPGA will be the slave. The STM32 has a configurable SPI module that is easily configurable unlike the FPGA. Futhermore, the MISO line is not needed because the FPGA does not send any big data to the STM32. The slave select line will operate as a write enable.
-
-
-
-### SPI
-
-The FPGA will configure as a slave of the SPI protocol. THe FPGA (Basys3) does not have a IP-Core that supports external SPI communication so the SPI slave has to be designed. The module requires three inputs as mentioned before in the [STM32](architecture.md#STM32) section.
-
-
-### PPU communication
-
-The SPI module will be configured that sends 8 bits per cycle and at a speed of 1.0 MB/s. The STM32 Cube IDE SPI module does not include a slave select line so a pin has to configured manually to fullfill this purpose. Every data transfer consists out of 4 times 8 bits, so 32 bits in total. The first byte is the address and the other 3 bytes consist the data.
-
-
-### SPI
-The FPGA uses 3 JMOD pins to receive the SPI data. The FPGA does not have a IP-Core for SPI. To receive the data the module has 3 synchronisers for the incoming SPI clock, data and slave select. The data will be read via the SPI protocol and shifted untill all 32 bits are read.
--
cgit v1.2.3