From f04ecca4077b5f8723b2a8e0a125bfeacc44214a Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 13:57:55 +0100 Subject: single frequency implementation --- basys3/basys3.srcs/apu_LUT_reader.vhd | 56 ++++++++++++++++++++++++++++++++ basys3/basys3.srcs/apu_tb_LUT_reader.vhd | 48 +++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 basys3/basys3.srcs/apu_LUT_reader.vhd create mode 100644 basys3/basys3.srcs/apu_tb_LUT_reader.vhd (limited to 'basys3') diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd new file mode 100644 index 0000000..2dd3b06 --- /dev/null +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -0,0 +1,56 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity apu_LUT_reader is + port ( + clk : in std_logic; + rst : in std_logic; + freq : in std_logic_vector(11 downto 0); + wave : in std_logic_vector(1 downto 0); + value : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture Behavioral of apu_LUT_reader is + + signal idx : std_logic_vector(7 downto 0) := (others => '0'); + signal buf : unsigned := (others => '0'); + +begin + + process (clk) + begin + if rst = '1' then + idx <= x"00"; + buf <= x"00"; + elsif rising_edge(clk) then + --main code here + + if wave = "00" then --Sawtooth + value <= idx; + elsif wave = "01" then --Square + if (signed(idx) < 128) then + value <= x"00"; + else + value <= x"FF"; + end if; + elsif wave = "10" then --Triangle + value <= std_logic_vector( abs(signed(idx)-127)*2 ); + else--wave = "11" then --Noise + --implement noise function here: + value <= x"80"; --remove this + end if; + + + + if unsigned(idx) < 255 then --moves to next index value + idx <= std_logic_vector( unsigned(idx) + '1'); + else + idx <= x"00"; + end if; + + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd new file mode 100644 index 0000000..d4ed935 --- /dev/null +++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity apu_tb_LUT_reader is +end entity; + +architecture Behavioral of apu_tb_LUT_reader is + component apu_LUT_reader is + port ( + clk : in std_logic; + rst : in std_logic; + freq : in std_logic_vector(11 downto 0); + wave : in std_logic_vector(1 downto 0); + value : out std_logic_vector(7 downto 0) + ); + end component; + + signal OK : boolean := false; + + signal clk : std_logic := '0'; + signal rst : std_logic := '0'; + signal freq : std_logic_vector(11 downto 0) := (others => '0'); + signal wave : std_logic_vector(1 downto 0) := (others => '0'); + +begin + + TB: process + begin + wave <= "00"; + for I in 0 to 255 loop + clk <= '1'; + + -- freq <= '1'; + + + wait for 1 ps; + clk <= '0'; + wait for 1 ps; + + + end loop; + end process; + +end architecture; \ No newline at end of file -- cgit v1.2.3 From 3739edf5d5adc7a79aa9fd050d45493d697eaa92 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 14:02:12 +0100 Subject: apu_LUT_reader made with variable frequency --- basys3/basys3.srcs/apu_LUT_reader.vhd | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index 2dd3b06..a37cd30 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -44,10 +44,15 @@ begin - if unsigned(idx) < 255 then --moves to next index value - idx <= std_logic_vector( unsigned(idx) + '1'); + if buf < unsigned(freq) then -- change frequency + buf <= buf + 1; else - idx <= x"00"; + buf <= x"00"; + if unsigned(idx) < 255 then --moves to next index value + idx <= std_logic_vector( unsigned(idx) + '1'); + else + idx <= x"00"; + end if; end if; end if; -- cgit v1.2.3 From e93383878d3784b390f0ab3a9514de6ce3dedb2a Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 15:55:37 +0100 Subject: polish on APU_N2F --- basys3/basys3.srcs/apu_note_to_frequency.vhd | 39 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 19 deletions(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd index 878da30..b8f561b 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd @@ -6,35 +6,36 @@ entity apu_note_to_frequency is port ( -- clk : in std_logic; -- rst : in std_logic; - data : in std_logic_vector(7 downto 0); - freq : out std_logic_vector(11 downto 0) --frequency + data : in std_logic_vector(6 downto 0); + freq : out std_logic_vector(11 downto 0) -- frequency ); end entity; architecture Behavioral of apu_note_to_frequency is signal buffSmall : std_logic_vector(7 downto 0) := (others => '0'); -signal buff : std_logic_vector(15 downto 0) := (others => '0'); +signal buff : std_logic_vector(11 downto 0) := (others => '0'); signal shift : integer; begin shift <= to_integer(unsigned( data(2 downto 0) )); - buffSmall <= - x"F0" when data(7 downto 3) = (x"C" & '0') else -- C 496 - x"D0" when data(7 downto 3) = (x"C" & '1') else -- C# 464 - x"B0" when data(7 downto 3) = (x"D" & '0') else -- D 432 - x"A0" when data(7 downto 3) = (x"D" & '1') else -- D# 416 - x"80" when data(7 downto 3) = (x"E" & '0') else -- E 384 - x"70" when data(7 downto 3) = (x"F" & '0') else -- F 368 - x"58" when data(7 downto 3) = (x"F" & '1') else -- F# 344 - x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320 - x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304 - x"20" when data(7 downto 3) = (x"A" & '0') else -- A 288 - x"10" when data(7 downto 3) = (x"A" & '1') else -- A# 272 - x"00" when data(7 downto 3) = (x"B" & '0') else -- B 256 - x"01"; + buff <= + x"1F0" when data(6 downto 3) = (x"1") else -- C 496 + x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464 + x"1B0" when data(6 downto 3) = (x"3") else -- D 432 + x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416 + x"180" when data(6 downto 3) = (x"5") else -- E 384 + x"170" when data(6 downto 3) = (x"6") else -- F 368 + x"158" when data(6 downto 3) = (x"7") else -- F#/Gb 344 + x"140" when data(6 downto 3) = (x"8") else -- G 320 + x"130" when data(6 downto 3) = (x"9") else -- G#/Ab 304 + x"120" when data(6 downto 3) = (x"A") else -- A 288 + x"110" when data(6 downto 3) = (x"B") else -- A#/Bb 272 + x"100" when data(6 downto 3) = (x"C") else -- B 256 + x"000"; - buff <= x"1" & buffSmall; - freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2) + -- buff <= x"1" & buffSmall; + freq <= std_logic_vector( shift_right(unsigned(buff), shift) ); + -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');) end architecture; \ No newline at end of file -- cgit v1.2.3 From f28e1ceec5b9a6ee3f156c3f032eb7a78a08f401 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 16:20:20 +0100 Subject: shifted triangle wave 180* --- basys3/basys3.srcs/apu_LUT_reader.vhd | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index a37cd30..e56f855 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -14,7 +14,10 @@ end entity; architecture Behavioral of apu_LUT_reader is - signal idx : std_logic_vector(7 downto 0) := (others => '0'); + constant AMPLITUDE : natural := 0; + constant SAMPLE_SIZE : natural := 256; + + signal idx : unsigned := (others => '0'); signal buf : unsigned := (others => '0'); begin @@ -25,21 +28,25 @@ begin idx <= x"00"; buf <= x"00"; elsif rising_edge(clk) then - --main code here + -- main code here - if wave = "00" then --Sawtooth - value <= idx; - elsif wave = "01" then --Square - if (signed(idx) < 128) then + if wave = "00" then -- Sawtooth + value <= std_logic_vector( idx ); + elsif wave = "01" then -- Square + if idx < (SAMPLE_SIZE/2) then value <= x"00"; else value <= x"FF"; end if; - elsif wave = "10" then --Triangle - value <= std_logic_vector( abs(signed(idx)-127)*2 ); - else--wave = "11" then --Noise - --implement noise function here: - value <= x"80"; --remove this + elsif wave = "10" then -- Triangle + if idx < (SAMPLE_SIZE/2) then + value <= std_logic_vector( idx*2 ); + else + value <= std_logic_vector( (SAMPLE_SIZE-idx)*2 ); + end if; + else-- wave = "11" then -- Noise + -- TODO: implement noise function here: + value <= x"80"; -- remove this end if; @@ -48,8 +55,8 @@ begin buf <= buf + 1; else buf <= x"00"; - if unsigned(idx) < 255 then --moves to next index value - idx <= std_logic_vector( unsigned(idx) + '1'); + if idx < (SAMPLE_SIZE-1) then -- moves to next index value + idx <= idx + 1; else idx <= x"00"; end if; @@ -58,4 +65,4 @@ begin end if; end process; -end architecture; \ No newline at end of file +end architecture; -- cgit v1.2.3 From c3b877f0503ce995bd79ed3f4eb74d7370839582 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 16:30:24 +0100 Subject: small formatting fix --- basys3/basys3.srcs/apu_LUT_reader.vhd | 5 +++-- basys3/basys3.srcs/apu_tb_LUT_reader.vhd | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/apu_LUT_reader.vhd b/basys3/basys3.srcs/apu_LUT_reader.vhd index e56f855..6039798 100644 --- a/basys3/basys3.srcs/apu_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_LUT_reader.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity apu_LUT_reader is port ( - clk : in std_logic; + clk : in std_logic; rst : in std_logic; freq : in std_logic_vector(11 downto 0); wave : in std_logic_vector(1 downto 0); @@ -27,6 +27,7 @@ begin if rst = '1' then idx <= x"00"; buf <= x"00"; + value <= x"00"; elsif rising_edge(clk) then -- main code here @@ -34,7 +35,7 @@ begin value <= std_logic_vector( idx ); elsif wave = "01" then -- Square if idx < (SAMPLE_SIZE/2) then - value <= x"00"; + value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave) else value <= x"FF"; end if; diff --git a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd index d4ed935..5a38d39 100644 --- a/basys3/basys3.srcs/apu_tb_LUT_reader.vhd +++ b/basys3/basys3.srcs/apu_tb_LUT_reader.vhd @@ -45,4 +45,4 @@ begin end loop; end process; -end architecture; \ No newline at end of file +end architecture; -- cgit v1.2.3 From 37e23f102d32d5c5894e4db07da529d51617cb89 Mon Sep 17 00:00:00 2001 From: NielsCoding Date: Thu, 23 Feb 2023 14:24:41 +0100 Subject: plut,comp en vga --- basys3/basys3.srcs/PPU_COMP_TB.vhd | 73 ++++++++++++++++++ basys3/basys3.srcs/ppu_comp.vhd | 67 +++++++++++++++++ basys3/basys3.srcs/ppu_plut.vhd | 99 +++++++++++++++++++++++++ basys3/basys3.srcs/ppu_vga_native.vhd | 122 +++++++++++++++++++++++++++++++ basys3/basys3.srcs/ppu_vga_native_tb.vhd | 116 +++++++++++++++++++++++++++++ basys3/basys3.srcs/ppu_vga_tiny.vhd | 83 +++++++++++++++++++++ 6 files changed, 560 insertions(+) create mode 100644 basys3/basys3.srcs/PPU_COMP_TB.vhd create mode 100644 basys3/basys3.srcs/ppu_comp.vhd create mode 100644 basys3/basys3.srcs/ppu_plut.vhd create mode 100644 basys3/basys3.srcs/ppu_vga_native.vhd create mode 100644 basys3/basys3.srcs/ppu_vga_native_tb.vhd create mode 100644 basys3/basys3.srcs/ppu_vga_tiny.vhd (limited to 'basys3') diff --git a/basys3/basys3.srcs/PPU_COMP_TB.vhd b/basys3/basys3.srcs/PPU_COMP_TB.vhd new file mode 100644 index 0000000..3733dab --- /dev/null +++ b/basys3/basys3.srcs/PPU_COMP_TB.vhd @@ -0,0 +1,73 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23.02.2023 12:23:00 +-- Design Name: +-- Module Name: PPU_COMP_TB - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +library UNISIM; +use work.ppu_consts.all; +use UNISIM.VComponents.all; + +entity PPU_COMP_TB is + +end PPU_COMP_TB; + +architecture Behavioral of PPU_COMP_TB is +COMPONENT ppu_comp + port ( + FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + BG_EN: out std_logic; + FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0)); +end component; + +signal FG_HIT: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0'); +signal BG_EN: std_logic := '0'; +signal FG_EN: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0'); +begin +UUT : ppu_comp port map ( +FG_HIT => FG_HIT, +BG_EN => BG_EN, +FG_EN => FG_EN +); + TB : PROCESS + BEGIN + FG_HIT <= (OTHERS => '0'); + wait for 1 ps; + FG_HIT(6) <= '1'; + FG_HIT(5) <= '1'; + FG_HIT(100) <= '1'; + wait for 1 ps; + + FG_HIT(0) <= '1'; + wait for 1 ps; + FG_HIT <= (OTHERS => '0'); + wait for 1 ps; + + + wait; + END PROCESS; +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_comp.vhd b/basys3/basys3.srcs/ppu_comp.vhd new file mode 100644 index 0000000..1ea315e --- /dev/null +++ b/basys3/basys3.srcs/ppu_comp.vhd @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23.02.2023 10:31:25 +-- Design Name: +-- Module Name: ppu_comp - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.ppu_consts.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ppu_comp is + Port ( + FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0); + BG_EN: out std_logic; + FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0)); + +end ppu_comp; + +architecture Behavioral of ppu_comp is +signal FG_HIT_Empty : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0'); +begin + process (FG_HIT) + variable HIT : BOOLEAN := FALSE; + begin + -- check if fg_hit is not empty + if FG_HIT /= FG_HIT_Empty then + BG_EN <= '0'; + FOR I IN 0 TO PPU_FG_SPRITE_COUNT-1 LOOP + -- if fg_hit is the first one then enable it + IF(FG_HIT(I) = '1' AND HIT = FALSE) THEN + FG_EN(I) <= '1'; + HIT := TRUE; + ELSE + -- make rest low + FG_EN(I) <= '0'; + END IF; + END LOOP; + HIT := FALSE; + else + BG_EN <= '1'; + FG_EN <= (others => '0'); + end if; + end process; +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_plut.vhd b/basys3/basys3.srcs/ppu_plut.vhd new file mode 100644 index 0000000..d03da1f --- /dev/null +++ b/basys3/basys3.srcs/ppu_plut.vhd @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23.02.2023 11:03:27 +-- Design Name: +-- Module Name: ppu_plut - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.ppu_consts.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use ieee.std_logic_unsigned.all; +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ppu_plut is + Port ( + CLK: in std_logic; -- system clock + CIDX: in std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- color in + RESET: in std_logic; + + -- internal memory block (AUX) + PAL_WEN: in std_logic; -- VRAM PAL write enable + PAL_ADDR: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- VRAM PAL address + PAL_DATA: in std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); -- VRAM PAL data + + R,G,B: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out +end ppu_plut; + +architecture Behavioral of ppu_plut is + component er_ram + generic( + ADDR_W : natural := PPU_PAL_ADDR_WIDTH; -- ADDR line width + DATA_W : natural := PPU_PAL_DATA_WIDTH; -- DATA line width + ADDR_LOW : natural := 16#0000#; -- starting address + ADDR_RANGE : natural := 16#0040#); -- amount of valid addresses after ADDR_LOW + port( + CLK : in std_logic; -- clock + RST : in std_logic; -- async memory clear + WEN : in std_logic; -- write enable + ADDR : in std_logic_vector(ADDR_W-1 downto 0); + DATA : in std_logic_vector(DATA_W-1 downto 0); + REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output + end component; + + SIGNAL PLUT : std_logic_vector((64 * PPU_PAL_DATA_WIDTH)-1 downto 0) := (others => '0'); + SIGNAL CHECK_ZERO_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');-- color in +begin + RAM : component er_ram port map( + CLK => CLK, + RST => RESET, + WEN => PAL_WEN, + ADDR => PAL_ADDR, + DATA => PAL_DATA, + REG => PLUT); + + + process(CLK,RESET) + VARIABLE COLOR : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0) := (others => '0');-- COLORS RGB IN + VARIABLE CIDX_INT : INTEGER := 0; + begin + IF(RESET = '1') THEN + PLUT <= (others => '0'); + ELSE + IF rising_edge (CLK) THEN + IF (CIDX /= CHECK_ZERO_CIDX) THEN + CIDX_INT := TO_INTEGER(UNSIGNED(CIDX)); + COLOR := PLUT((12 * CIDX_INT) + 11 DOWNTO (12*CIDX_INT)); + R <= COLOR(11 DOWNTO 8); + G <= COLOR(7 DOWNTO 4); + B <= COLOR(3 DOWNTO 0); + ELSE + R <= X"0"; + G <= X"0"; + B <= X"0"; + END IF; + END IF; + END IF; + end process; + +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_vga_native.vhd b/basys3/basys3.srcs/ppu_vga_native.vhd new file mode 100644 index 0000000..b337786 --- /dev/null +++ b/basys3/basys3.srcs/ppu_vga_native.vhd @@ -0,0 +1,122 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22.02.2023 13:20:47 +-- Design Name: +-- Module Name: ppu_vga_native - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.ppu_consts.all; + +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ppu_vga_native is + Port ( CLK: in std_logic; -- system clock + RESET: in std_logic; + + X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + PREADY: in std_logic; -- current pixel ready (pixel color is stable) + RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in + + RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out + VSYNC, HSYNC: out std_logic); -- VGA sync outputs +end ppu_vga_native; + +architecture Behavioral of ppu_vga_native is + type line_buffer is array(319 downto 0) of std_logic_vector(11 downto 0); + signal ram_x0 : line_buffer; -- buffer 0 + signal ram_x1: line_buffer; -- buffer 1 + signal hcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0'); + signal vcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0'); + signal rgb_out : STD_LOGIC_VECTOR(11 downto 0):= (others => '0'); -- output colors + signal px : integer; -- conversion for hcount + signal py :integer; -- conversion for vcount + signal bufferFilledOnbuffer0 : integer; + signal bufferFilledOnbuffer1 :integer; +begin + process (clk, x, y) + variable v_x : integer ; -- integer to hold vector X + begin + if rising_edge(clk) then + + v_x := TO_INTEGER(unsigned(x) - 72); + if(v_x >= 0 and v_x < 320 and PREADY = '1') then + if(y(0) = '0') then + ram_x0(v_x) <= RI & GI & BI; + if v_x = 319 then + bufferFilledOnbuffer0 <= TO_INTEGER(unsigned(y) - 14); + end if; + else + ram_x1(v_x) <= RI & GI & BI; + if v_x = 319 then + bufferFilledOnbuffer1 <= TO_INTEGER(unsigned(y) - 14); + end if; + end if; + end if; + -- T display(display data) + if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then + px <= TO_INTEGER(unsigned(hcount) - 144); + py <= TO_INTEGER(unsigned(vcount) - 31); + if(bufferFilledonBuffer0 = (py/2)) then + rgb_out <= ram_x0(px/2); + elsif(bufferFilledonbuffer1 = (py/2)) then + rgb_out <= ram_x1(px/2); + + else + rgb_out <= (others => '0'); + + end if; + end if; + -- pulse width + hsync <= '1'; + if hcount < 97 then + hsync <= '0'; + end if; + + vsync <= '1'; + if vcount < 3 then + vsync <= '0'; + end if; + + -- sync pulse time + hcount <= hcount + 1; + + if hcount = 800 then + vcount <= vcount + 1; + hcount <= (others => '0'); + end if; + + if vcount = 521 then + vcount <= (others => '0'); + end if; + + end if; + -- output colors + RO <= rgb_out(11 downto 8); + GO <= rgb_out(7 downto 4); + BO <= rgb_out(3 downto 0); + end process; + +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_vga_native_tb.vhd b/basys3/basys3.srcs/ppu_vga_native_tb.vhd new file mode 100644 index 0000000..3a225d8 --- /dev/null +++ b/basys3/basys3.srcs/ppu_vga_native_tb.vhd @@ -0,0 +1,116 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22.02.2023 13:28:57 +-- Design Name: +-- Module Name: ppu_vga_native_tb - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.ppu_consts.all; + +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity ppu_vga_native_tb is +end ppu_vga_native_tb; + +architecture Behavioral of ppu_vga_native_tb is +component ppu_vga_native + Port ( CLK: in std_logic; -- system clock + RESET: in std_logic; + + X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + PREADY: in std_logic; -- current pixel ready (pixel color is stable) + RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in + + RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out + VSYNC, HSYNC: out std_logic); -- VGA sync outputs +end component; +signal clk : std_logic := '0'; +signal rst : std_logic := '0'; +signal Pready : std_logic := '0'; + +signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0'); + +signal Xas : integer := 72; +signal Yas : integer := 14; +signal counter : std_logic_vector(1 downto 0) := (others => '0'); +signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0'); +signal RI,GI,BI: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color in +signal RO,GO,BO: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color out +signal VSYNC, HSYNC: std_logic := '0'; +begin + +UUT : ppu_vga_native port map( + clk => clk, + reset => rst, + x => x, + y => y, + pready => pready, + ri => ri, + gi => gi, + bi => bi, + ro => ro, + go => go, + bo => bo, + vsync => vsync, + hsync => hsync +); + + tb : process + begin + clk <= '1'; + wait for 1 ps; + clk <= '0'; + wait for 1 ps; + end process; + + + process(clk) + begin + if rising_edge(clk) then + counter <= counter + 1; + end if; + + if(counter = "11") then + pready <= '1'; + ri <= x"d"; + gi <= x"a"; + bi <= x"d"; + x <= std_logic_vector(to_unsigned(Xas, x'length)); + if (Xas = 391) then + Xas <= 72; + y <= std_logic_vector(to_unsigned(Yas, y'length)); + if (Yas = 255) then + Yas <= 14; + else + Yas <= Yas + 1; + end if; + else + Xas <= Xas + 1; + end if; + end if; + end process; +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd new file mode 100644 index 0000000..0132d7c --- /dev/null +++ b/basys3/basys3.srcs/ppu_vga_tiny.vhd @@ -0,0 +1,83 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22.02.2023 13:13:03 +-- Design Name: +-- Module Name: ppu_vga_tiny - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.ppu_consts.all; + +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ppu_vga_tiny is + Port ( + CLK: in std_logic; -- system clock + RESET: in std_logic; + + X: out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x + Y: out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y + + VSYNC, VBLANK, + HSYNC, HBLANK: out std_logic); -- VGA sync outputs + +end ppu_vga_tiny; + +architecture Behavioral of ppu_vga_tiny is + signal hcount: STD_LOGIC_VECTOR(PPU_POS_H_WIDTH-1 downto 0):= (others => '0'); + signal vcount: STD_LOGIC_VECTOR(PPU_POS_V_WIDTH-1 downto 0):= (others => '0'); + +begin +process (CLK) +begin + if rising_edge(CLK) then + -- x,y data uit + X <= hcount; + Y <= vcount; + --pulse width + if hcount < 32 then + hsync <= '0'; + else + hsync <= '1'; + end if; + + if vcount < 8 then + vsync <= '0'; + else + vsync <= '1'; + end if; + -- sync pulse time + hcount <= hcount + 1; + + if hcount = 400 then + vcount <= vcount + 1; + hcount <= (others => '0'); + end if; + + if vcount = 255 then + vcount <= (others => '0'); + end if; + end if; +end process; + +end Behavioral; -- cgit v1.2.3 From cc225651e767340075cc77397c4541860847b31f Mon Sep 17 00:00:00 2001 From: heavydemon21 Date: Thu, 23 Feb 2023 16:01:41 +0100 Subject: clock interne clcok toegevoegd aan de vga modules. niks is veranderd aan de PLUT want die werkt nog steeds op dezelfde SYSCLK. --- basys3/basys3.srcs/ppu_vga_native.vhd | 109 +++++++++++++++++----------------- basys3/basys3.srcs/ppu_vga_tiny.vhd | 67 +++++++++++++-------- 2 files changed, 99 insertions(+), 77 deletions(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/ppu_vga_native.vhd b/basys3/basys3.srcs/ppu_vga_native.vhd index b337786..f5d9809 100644 --- a/basys3/basys3.srcs/ppu_vga_native.vhd +++ b/basys3/basys3.srcs/ppu_vga_native.vhd @@ -50,6 +50,7 @@ architecture Behavioral of ppu_vga_native is signal ram_x1: line_buffer; -- buffer 1 signal hcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0'); signal vcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0'); + signal clkCounter: STD_LOGIC_VECTOR(1 downto 0):= (others => '0'); signal rgb_out : STD_LOGIC_VECTOR(11 downto 0):= (others => '0'); -- output colors signal px : integer; -- conversion for hcount signal py :integer; -- conversion for vcount @@ -60,63 +61,65 @@ begin variable v_x : integer ; -- integer to hold vector X begin if rising_edge(clk) then - - v_x := TO_INTEGER(unsigned(x) - 72); - if(v_x >= 0 and v_x < 320 and PREADY = '1') then - if(y(0) = '0') then - ram_x0(v_x) <= RI & GI & BI; - if v_x = 319 then - bufferFilledOnbuffer0 <= TO_INTEGER(unsigned(y) - 14); - end if; - else - ram_x1(v_x) <= RI & GI & BI; - if v_x = 319 then - bufferFilledOnbuffer1 <= TO_INTEGER(unsigned(y) - 14); + clkCounter <= clkCounter + 1; + if(clkCounter = "11")then + v_x := TO_INTEGER(unsigned(x) - 72); + if(v_x >= 0 and v_x < 320 and PREADY = '1') then + if(y(0) = '0') then + ram_x0(v_x) <= RI & GI & BI; + if v_x = 319 then + bufferFilledOnbuffer0 <= TO_INTEGER(unsigned(y) - 14); + end if; + else + ram_x1(v_x) <= RI & GI & BI; + if v_x = 319 then + bufferFilledOnbuffer1 <= TO_INTEGER(unsigned(y) - 14); + end if; + end if; + end if; + -- T display(display data) + if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then + px <= TO_INTEGER(unsigned(hcount) - 144); + py <= TO_INTEGER(unsigned(vcount) - 31); + if(bufferFilledonBuffer0 = (py/2)) then + rgb_out <= ram_x0(px/2); + elsif(bufferFilledonbuffer1 = (py/2)) then + rgb_out <= ram_x1(px/2); + + else + rgb_out <= (others => '0'); + end if; - end if; - end if; - -- T display(display data) - if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then - px <= TO_INTEGER(unsigned(hcount) - 144); - py <= TO_INTEGER(unsigned(vcount) - 31); - if(bufferFilledonBuffer0 = (py/2)) then - rgb_out <= ram_x0(px/2); - elsif(bufferFilledonbuffer1 = (py/2)) then - rgb_out <= ram_x1(px/2); - - else - rgb_out <= (others => '0'); - + end if; + -- pulse width + hsync <= '1'; + if hcount < 97 then + hsync <= '0'; + end if; + + vsync <= '1'; + if vcount < 3 then + vsync <= '0'; + end if; + + -- sync pulse time + hcount <= hcount + 1; + + if hcount = 800 then + vcount <= vcount + 1; + hcount <= (others => '0'); + end if; + + if vcount = 521 then + vcount <= (others => '0'); end if; end if; - -- pulse width - hsync <= '1'; - if hcount < 97 then - hsync <= '0'; - end if; - - vsync <= '1'; - if vcount < 3 then - vsync <= '0'; - end if; - - -- sync pulse time - hcount <= hcount + 1; - - if hcount = 800 then - vcount <= vcount + 1; - hcount <= (others => '0'); - end if; - - if vcount = 521 then - vcount <= (others => '0'); - end if; - + + -- output colors + RO <= rgb_out(11 downto 8); + GO <= rgb_out(7 downto 4); + BO <= rgb_out(3 downto 0); end if; - -- output colors - RO <= rgb_out(11 downto 8); - GO <= rgb_out(7 downto 4); - BO <= rgb_out(3 downto 0); end process; end Behavioral; diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd index 0132d7c..7b1703e 100644 --- a/basys3/basys3.srcs/ppu_vga_tiny.vhd +++ b/basys3/basys3.srcs/ppu_vga_tiny.vhd @@ -46,37 +46,56 @@ end ppu_vga_tiny; architecture Behavioral of ppu_vga_tiny is signal hcount: STD_LOGIC_VECTOR(PPU_POS_H_WIDTH-1 downto 0):= (others => '0'); signal vcount: STD_LOGIC_VECTOR(PPU_POS_V_WIDTH-1 downto 0):= (others => '0'); + signal CLKcounter: STD_LOGIC_VECTOR(4 downto 0):= (others => '0'); begin process (CLK) begin if rising_edge(CLK) then - -- x,y data uit + CLKcounter <= CLKcounter + 1; + if(CLKcounter > 15) then + -- x,y data uit X <= hcount; Y <= vcount; - --pulse width - if hcount < 32 then - hsync <= '0'; - else - hsync <= '1'; - end if; - - if vcount < 8 then - vsync <= '0'; - else - vsync <= '1'; - end if; - -- sync pulse time - hcount <= hcount + 1; - - if hcount = 400 then - vcount <= vcount + 1; - hcount <= (others => '0'); - end if; - - if vcount = 255 then - vcount <= (others => '0'); - end if; + + --pulse width + if hcount < 32 or hcount >= 320-80 then + hsync <= '0'; + else + hsync <= '1'; + end if; + + if vcount < 8 or vcount >= 240-15 then + vsync <= '0'; + else + vsync <= '1'; + end if; + + -- Hblank and Vblank outputs + if hcount >= 320-80 then + hblank <= '1'; + else + hblank <= '0'; + end if; + + if vcount >= 240-15 then + vblank <= '1'; + else + vblank <= '0'; + end if; + + -- sync pulse time + hcount <= hcount + 1; + + if hcount = 400 then + vcount <= vcount + 1; + hcount <= (others => '0'); + end if; + + if vcount = 255 then + vcount <= (others => '0'); + end if; + end if; end if; end process; -- cgit v1.2.3 From b2190241fccdfbf28d6068c9f0d2179aec285528 Mon Sep 17 00:00:00 2001 From: heavydemon21 Date: Thu, 23 Feb 2023 16:11:29 +0100 Subject: aanpassingen was counter naar 0 vergeten --- basys3/basys3.srcs/ppu_vga_tiny.vhd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'basys3') diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd index 7b1703e..f47df48 100644 --- a/basys3/basys3.srcs/ppu_vga_tiny.vhd +++ b/basys3/basys3.srcs/ppu_vga_tiny.vhd @@ -54,6 +54,7 @@ begin if rising_edge(CLK) then CLKcounter <= CLKcounter + 1; if(CLKcounter > 15) then + clkCounter <= (others => '0'); -- x,y data uit X <= hcount; Y <= vcount; @@ -91,7 +92,7 @@ begin vcount <= vcount + 1; hcount <= (others => '0'); end if; - + if vcount = 255 then vcount <= (others => '0'); end if; -- cgit v1.2.3