From 77870488404563df2c18e4ec4719e767fff98919 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Mon, 20 Feb 2023 13:11:21 +0100 Subject: PPU AUX memory finished and tested --- basys3/basys3.srcs/er_ram.vhd | 2 +- basys3/basys3.srcs/ppu_aux.vhd | 52 ++++++++++++++++++++ basys3/basys3.srcs/ppu_aux_tb.vhd | 100 ++++++++++++++++++++++++++++++++++++++ basys3/basys3.srcs/ppu_consts.vhd | 2 +- basys3/basys3.xpr | 18 +++++-- 5 files changed, 169 insertions(+), 5 deletions(-) create mode 100644 basys3/basys3.srcs/ppu_aux.vhd create mode 100644 basys3/basys3.srcs/ppu_aux_tb.vhd (limited to 'basys3') diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd index a35514c..f106d4e 100644 --- a/basys3/basys3.srcs/er_ram.vhd +++ b/basys3/basys3.srcs/er_ram.vhd @@ -15,7 +15,7 @@ entity er_ram is -- exposed register RAM WEN : in std_logic; -- write enable ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- address line DATA : in std_logic_vector(DATA_W-1 downto 0); -- data input - REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0)); -- exposed register output + REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output end er_ram; architecture Behavioral of er_ram is diff --git a/basys3/basys3.srcs/ppu_aux.vhd b/basys3/basys3.srcs/ppu_aux.vhd new file mode 100644 index 0000000..9062bc4 --- /dev/null +++ b/basys3/basys3.srcs/ppu_aux.vhd @@ -0,0 +1,52 @@ +library ieee; +library work; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +use work.ppu_consts.all; + +entity ppu_aux is port( + CLK : in std_logic; -- system clock + RESET : in std_logic; -- reset memory + + -- internal memory block (AUX) + AUX_WEN : in std_logic; -- VRAM AUX write enable + AUX_ADDR : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address + AUX_DATA : in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data + + -- aux outputs + BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + FG_FETCH : out std_logic); +end ppu_aux; + +architecture Behavioral of ppu_aux is + component er_ram + generic( + ADDR_W : natural := PPU_AUX_ADDR_WIDTH; -- ADDR line width + DATA_W : natural := PPU_AUX_DATA_WIDTH; -- DATA line width + ADDR_LOW : natural := 16#0000#; -- starting address + ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW + port( + CLK : in std_logic; -- clock + RST : in std_logic; -- async memory clear + WEN : in std_logic; -- write enable + ADDR : in std_logic_vector(ADDR_W-1 downto 0); + DATA : in std_logic_vector(DATA_W-1 downto 0); + REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output + end component; + + signal INT_REG : std_logic_vector(2 * PPU_AUX_DATA_WIDTH - 1 downto 0); +begin + -- docs/architecture.md#auxiliary-memory + FG_FETCH <= INT_REG(17); + BG_SHIFT_X <= INT_REG(16 downto 8); + BG_SHIFT_Y <= INT_REG(7 downto 0); + + RAM : component er_ram port map( + CLK => CLK, + RST => RESET, + WEN => AUX_WEN, + ADDR => AUX_ADDR, + DATA => AUX_DATA, + REG => INT_REG); +end Behavioral; diff --git a/basys3/basys3.srcs/ppu_aux_tb.vhd b/basys3/basys3.srcs/ppu_aux_tb.vhd new file mode 100644 index 0000000..ab3db62 --- /dev/null +++ b/basys3/basys3.srcs/ppu_aux_tb.vhd @@ -0,0 +1,100 @@ +library ieee; +library unisim; +library work; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; +use work.ppu_consts.all; + +entity ppu_aux_tb is +end ppu_aux_tb; + +architecture behavioral of ppu_aux_tb is + component ppu_aux port( + CLK : in std_logic; -- system clock + RESET : in std_logic; -- reset memory + + -- internal memory block (AUX) + AUX_WEN : in std_logic; -- VRAM AUX write enable + AUX_ADDR : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address + AUX_DATA : in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data + + -- aux outputs + BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + FG_FETCH : out std_logic); + end component; + + signal CLK, RST, WEN : std_logic := '0'; + signal ADDR : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0) := (others => '0'); + signal DATA : std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0) := (others => '0'); + + signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); + signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); + signal FG_FETCH : std_logic; +begin + uut : component ppu_aux + port map( + CLK => CLK, + RESET => RST, + AUX_WEN => WEN, + AUX_ADDR => ADDR, + AUX_DATA => DATA, + BG_SHIFT_X => BG_SHIFT_X, + BG_SHIFT_Y => BG_SHIFT_Y, + FG_FETCH => FG_FETCH); + + tb : process + begin + -- reset + RST <= '1'; + wait for 5 ns; + RST <= '0'; + wait for 5 ns; + + WEN <= '1'; + -- set BG_SHIFT_X to 178 + -- set BG_SHIFT_Y to 39 + -- set FG_FETCH to 1 + ADDR(0) <= '0'; + DATA <= x"b327"; + + CLK <= '1'; + wait for 1 ns; + CLK <= '0'; + wait for 1 ns; + + ADDR(0) <= '1'; + DATA <= x"0002"; + + CLK <= '1'; + wait for 1 ns; + CLK <= '0'; + wait for 1 ns; + + wait for 5 ns; + + -- set BG_SHIFT_X to 30 + -- set BG_SHIFT_Y to 69 + -- set FG_FETCH to 0 + ADDR(0) <= '0'; + DATA <= x"1e45"; + + CLK <= '1'; + wait for 1 ns; + CLK <= '0'; + wait for 1 ns; + + ADDR(0) <= '1'; + DATA <= x"0000"; + + CLK <= '1'; + wait for 1 ns; + CLK <= '0'; + wait for 1 ns; + + + wait; -- stop for simulator + end process; +end; diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd index 3e7d46d..ab2ccf1 100644 --- a/basys3/basys3.srcs/ppu_consts.vhd +++ b/basys3/basys3.srcs/ppu_consts.vhd @@ -14,7 +14,7 @@ package ppu_consts is constant PPU_FAM_DATA_WIDTH : natural := 16; constant PPU_PAL_ADDR_WIDTH : natural := 6; constant PPU_PAL_DATA_WIDTH : natural := 12; - constant PPU_AUX_ADDR_WIDTH : natural := 2; + constant PPU_AUX_ADDR_WIDTH : natural := 1; constant PPU_AUX_DATA_WIDTH : natural := 16; constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index a63514c..90e7823 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -61,7 +61,7 @@