From d2eb1cf5055a19f3e276ce737428b06332de63b3 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 11:23:30 +0100
Subject: rename .vhdl to .vhd

---
 basys3/basys3.xpr | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 466cc1f..d5ba760 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -44,6 +44,7 @@
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
     <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -96,19 +97,19 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu_addr_dec.vhdl">
+      <File Path="$PSRCDIR/ppu_pceg.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu_pceg.vhdl">
+      <File Path="$PSRCDIR/ppu.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu.vhd">
+      <File Path="$PSRCDIR/ppu_addr_dec.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -117,7 +118,6 @@
       <File Path="$PSRCDIR/apu.vhd">
         <FileInfo>
           <Attr Name="UserDisabled" Val="1"/>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -125,7 +125,6 @@
       <File Path="$PSRCDIR/apu_note_to_frequency.vhd">
         <FileInfo>
           <Attr Name="UserDisabled" Val="1"/>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -144,15 +143,14 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/ppu_addr_dec_tb.vhdl">
+      <File Path="$PSRCDIR/ppu_addr_dec_tb.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/ppu_pceg_tb.vhdl">
+      <File Path="$PSRCDIR/ppu_pceg_tb.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -160,7 +158,6 @@
       <File Path="$PSRCDIR/apu_note_to_frequency_tb.vhd">
         <FileInfo>
           <Attr Name="UserDisabled" Val="1"/>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-- 
cgit v1.2.3


From 62899050c3d0fb7e438c403f707add9218a2c928 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 12:37:59 +0100
Subject: exposed ram module implemented

---
 basys3/basys3.srcs/er_ram.vhd                      |  53 ++++++++++
 basys3/basys3.srcs/er_ram_mod.vhd                  |  34 ++++++
 basys3/basys3.srcs/er_ram_mod_tb.vhd               |  81 ++++++++++++++
 basys3/basys3.srcs/er_ram_tb.vhd                   | 116 +++++++++++++++++++++
 .../basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci   |   2 +-
 .../basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci   |   2 +-
 basys3/basys3.xpr                                  |  49 +++++++--
 7 files changed, 325 insertions(+), 12 deletions(-)
 create mode 100644 basys3/basys3.srcs/er_ram.vhd
 create mode 100644 basys3/basys3.srcs/er_ram_mod.vhd
 create mode 100644 basys3/basys3.srcs/er_ram_mod_tb.vhd
 create mode 100644 basys3/basys3.srcs/er_ram_tb.vhd

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd
new file mode 100644
index 0000000..a35514c
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram.vhd
@@ -0,0 +1,53 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity er_ram is -- exposed register RAM
+	generic(
+		ADDR_W : natural := 2; -- ADDR line width
+		DATA_W : natural := 2; -- DATA line width
+		ADDR_LOW : natural := 16#0000#; -- starting address
+		ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
+	port(
+		CLK : in std_logic; -- clock
+		RST : in std_logic; -- async memory clear
+		WEN : in std_logic; -- write enable
+		ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- address line
+		DATA : in std_logic_vector(DATA_W-1 downto 0); -- data input
+		REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0)); -- exposed register output
+end er_ram;
+
+architecture Behavioral of er_ram is
+	component er_ram_mod
+		generic(
+			W : natural := 1; -- module data width
+			ADDR_W : natural := 1; -- address width
+			ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+		port(
+			CLK : in std_logic; -- clock
+			RST : in std_logic; -- async memory clear
+			WEN : in std_logic; -- write enable
+			ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+			DATA : in std_logic_vector(W-1 downto 0); -- data
+			REG : out std_logic_vector(W-1 downto 0)); -- direct register out
+	end component;
+	signal INT_REG : std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0);
+begin
+	REG <= INT_REG;
+
+	registers : for idx in ADDR_LOW to ADDR_LOW + ADDR_RANGE - 1 generate
+		reg : component er_ram_mod
+			generic map(
+				W => DATA_W,
+				ADDR_W => ADDR_W,
+				ADDR_M => std_logic_vector(to_unsigned(idx, ADDR_W)))
+			port map(
+				CLK => CLK,
+				RST => RST,
+				WEN => WEN,
+				ADDR => ADDR,
+				DATA => DATA,
+				REG => INT_REG(idx*DATA_W+DATA_W-1 downto idx*DATA_W));
+	end generate;
+end Behavioral;
diff --git a/basys3/basys3.srcs/er_ram_mod.vhd b/basys3/basys3.srcs/er_ram_mod.vhd
new file mode 100644
index 0000000..ae680b1
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_mod.vhd
@@ -0,0 +1,34 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+
+entity er_ram_mod is -- exposed register RAM module (single register)
+	generic(
+		W : natural := 1; -- module data width
+		ADDR_W : natural := 1; -- address width
+		ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+	port(
+		CLK : in std_logic; -- clock
+		RST : in std_logic; -- async memory clear
+		WEN : in std_logic; -- write enable
+		ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- RAM address line
+		DATA : in std_logic_vector(W-1 downto 0); -- RAM input data line
+		REG : out std_logic_vector(W-1 downto 0)); -- direct register output lines
+end er_ram_mod;
+
+architecture Behavioral of er_ram_mod is
+	signal DATA_REG : std_logic_vector(W-1 downto 0);
+begin
+	REG <= DATA_REG;
+
+	process(CLK, RST)
+	begin
+		if RST = '1' then
+			DATA_REG <= (others => '0');
+		elsif rising_edge(CLK) then
+			if WEN = '1' and ADDR = ADDR_M then
+				DATA_REG <= DATA;
+			end if;
+		end if;
+	end process;
+end Behavioral;
diff --git a/basys3/basys3.srcs/er_ram_mod_tb.vhd b/basys3/basys3.srcs/er_ram_mod_tb.vhd
new file mode 100644
index 0000000..aa77a56
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_mod_tb.vhd
@@ -0,0 +1,81 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity er_ram_mod_tb is
+end er_ram_mod_tb;
+
+architecture behavioral of er_ram_mod_tb is
+	component er_ram_mod
+		generic(
+			W : natural := 1; -- module data width
+			ADDR_W : natural := 1; -- address width
+			ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
+		port(
+			CLK : in std_logic; -- clock
+			RST : in std_logic; -- async memory clear
+			WEN : in std_logic; -- write enable
+			ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+			DATA : in std_logic_vector(W-1 downto 0); -- data
+			REG : out std_logic_vector(W-1 downto 0)); -- direct register out
+	end component;
+
+	signal CLK, RST, WEN : std_logic := '0';
+	signal ADDR : std_logic_vector(3 downto 0);
+	signal DATA : std_logic_vector(7 downto 0);
+	signal REG : std_logic_vector(7 downto 0);
+begin
+	uut : component er_ram_mod
+		generic map(
+			W => 8,
+			ADDR_W => 4,
+			ADDR_M => x"5")
+		port map(
+			CLK => CLK,
+			RST => RST,
+			WEN => WEN,
+			ADDR => ADDR,
+			DATA => DATA,
+			REG => REG);
+
+	tb : process
+	begin
+		wait for 5 ns;
+
+		-- async reset (safety)
+		RST <= '1';
+		wait for 5 ns;
+		RST <= '0';
+		wait for 5 ns;
+
+		-- set 0xef at address 0x5 (exists)
+		DATA <= x"ef";
+		ADDR <= x"5";
+		WEN <= '1';
+
+		CLK <= '1';
+		wait for 5 ns;
+		CLK <= '0';
+		wait for 5 ns;
+
+		-- set 0x34 at address 0x4 (doesn't exist)
+		ADDR <= x"4";
+		DATA <= x"34";
+
+		CLK <= '1';
+		wait for 5 ns;
+		CLK <= '0';
+		wait for 5 ns;
+
+		-- reset
+		RST <= '1';
+		wait for 5 ns;
+		RST <= '0';
+		wait for 5 ns;
+
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/basys3/basys3.srcs/er_ram_tb.vhd b/basys3/basys3.srcs/er_ram_tb.vhd
new file mode 100644
index 0000000..d360442
--- /dev/null
+++ b/basys3/basys3.srcs/er_ram_tb.vhd
@@ -0,0 +1,116 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity er_ram_tb is
+end er_ram_tb;
+
+architecture behavioral of er_ram_tb is
+	component er_ram
+		generic(
+			ADDR_W : natural := 2; -- ADDR line width
+			DATA_W : natural := 2; -- DATA line width
+			ADDR_LOW : natural := 16#0000#; -- starting address
+			ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
+		port(
+			CLK : in std_logic; -- clock
+			RST : in std_logic; -- async memory clear
+			WEN : in std_logic; -- write enable
+			ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+			DATA : in std_logic_vector(DATA_W-1 downto 0);
+			REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0));
+	end component;
+
+	signal CLK, RST, WEN : std_logic := '0';
+	signal ADDR : std_logic_vector(3 downto 0);
+	signal DATA : std_logic_vector(7 downto 0);
+	signal REG : std_logic_vector(31 downto 0);
+begin
+	uut : component er_ram
+		generic map(
+			ADDR_W => 4,
+			DATA_W => 8,
+			ADDR_LOW => 0,
+			ADDR_RANGE => 4)
+		port map(
+			CLK => CLK,
+			RST => RST,
+			WEN => WEN,
+			ADDR => ADDR,
+			DATA => DATA,
+			REG => REG);
+
+	tb : process
+	begin
+		wait for 5 ns;
+
+		-- async reset (safety)
+		RST <= '1';
+		wait for 5 ns;
+		RST <= '0';
+		wait for 5 ns;
+
+		-- set 0xef at address 0x1 (exists)
+		DATA <= x"ef";
+		ADDR <= x"1";
+		WEN <= '1';
+
+		CLK <= '1';
+		wait for 5 ns;
+		CLK <= '0';
+		wait for 5 ns;
+
+		-- set 0x34 at address 0x4 (doesn't exist)
+		ADDR <= x"4";
+		DATA <= x"34";
+
+		CLK <= '1';
+		wait for 5 ns;
+		CLK <= '0';
+		wait for 5 ns;
+
+		-- reset
+		RST <= '1';
+		wait for 5 ns;
+		RST <= '0';
+		wait for 5 ns;
+
+		-- set REG to 0x12345678
+		ADDR <= x"0";
+		DATA <= x"12";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		ADDR <= x"1";
+		DATA <= x"34";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		ADDR <= x"2";
+		DATA <= x"56";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		ADDR <= x"3";
+		DATA <= x"78";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
index f5e1696..e299ea1 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_bam/ppu_bam.xci
@@ -163,7 +163,7 @@
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7a35t" } ],
         "PACKAGE": [ { "value": "cpg236" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
index 51914b1..24d2b58 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
@@ -163,7 +163,7 @@
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7a35t" } ],
         "PACKAGE": [ { "value": "cpg236" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-1" } ],
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index d5ba760..a63514c 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -42,6 +42,7 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
     <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
     <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
     <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
@@ -60,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="12"/>
+    <Option Name="WTXSimLaunchSim" Val="15"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -98,19 +99,19 @@
         </FileInfo>
       </File>
       <File Path="$PSRCDIR/ppu_pceg.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PSRCDIR/ppu.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PSRCDIR/ppu_addr_dec.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -129,9 +130,21 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/er_ram.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/er_ram_mod.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu"/>
+        <Option Name="TopModule" Val="er_ram"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -144,13 +157,13 @@
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/ppu_addr_dec_tb.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PSRCDIR/ppu_pceg_tb.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -162,9 +175,21 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/er_ram_mod_tb.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/er_ram_tb.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_addr_dec_tb"/>
+        <Option Name="TopModule" Val="er_ram_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -233,7 +258,9 @@
   <Runs Version="1" Minor="19">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
@@ -262,7 +289,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
-- 
cgit v1.2.3


From 77870488404563df2c18e4ec4719e767fff98919 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 13:11:21 +0100
Subject: PPU AUX memory finished and tested

---
 basys3/basys3.srcs/er_ram.vhd     |   2 +-
 basys3/basys3.srcs/ppu_aux.vhd    |  52 ++++++++++++++++++++
 basys3/basys3.srcs/ppu_aux_tb.vhd | 100 ++++++++++++++++++++++++++++++++++++++
 basys3/basys3.srcs/ppu_consts.vhd |   2 +-
 basys3/basys3.xpr                 |  18 +++++--
 5 files changed, 169 insertions(+), 5 deletions(-)
 create mode 100644 basys3/basys3.srcs/ppu_aux.vhd
 create mode 100644 basys3/basys3.srcs/ppu_aux_tb.vhd

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd
index a35514c..f106d4e 100644
--- a/basys3/basys3.srcs/er_ram.vhd
+++ b/basys3/basys3.srcs/er_ram.vhd
@@ -15,7 +15,7 @@ entity er_ram is -- exposed register RAM
 		WEN : in std_logic; -- write enable
 		ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- address line
 		DATA : in std_logic_vector(DATA_W-1 downto 0); -- data input
-		REG : out std_logic_vector((ADDR_W*DATA_W)-1 downto 0)); -- exposed register output
+		REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output
 end er_ram;
 
 architecture Behavioral of er_ram is
diff --git a/basys3/basys3.srcs/ppu_aux.vhd b/basys3/basys3.srcs/ppu_aux.vhd
new file mode 100644
index 0000000..9062bc4
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_aux.vhd
@@ -0,0 +1,52 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity ppu_aux is port(
+	CLK : in std_logic; -- system clock
+	RESET : in std_logic; -- reset memory
+
+	-- internal memory block (AUX)
+	AUX_WEN : in std_logic; -- VRAM AUX write enable
+	AUX_ADDR : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address
+	AUX_DATA : in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data
+	
+	-- aux outputs
+	BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+	BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+	FG_FETCH : out std_logic);
+end ppu_aux;
+
+architecture Behavioral of ppu_aux is
+	component er_ram
+		generic(
+			ADDR_W : natural := PPU_AUX_ADDR_WIDTH; -- ADDR line width
+			DATA_W : natural := PPU_AUX_DATA_WIDTH; -- DATA line width
+			ADDR_LOW : natural := 16#0000#; -- starting address
+			ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
+		port(
+			CLK : in std_logic; -- clock
+			RST : in std_logic; -- async memory clear
+			WEN : in std_logic; -- write enable
+			ADDR : in std_logic_vector(ADDR_W-1 downto 0);
+			DATA : in std_logic_vector(DATA_W-1 downto 0);
+			REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output
+	end component;
+
+	signal INT_REG : std_logic_vector(2 * PPU_AUX_DATA_WIDTH - 1 downto 0);
+begin
+	-- docs/architecture.md#auxiliary-memory
+	FG_FETCH <= INT_REG(17);
+	BG_SHIFT_X <= INT_REG(16 downto 8);
+	BG_SHIFT_Y <= INT_REG(7 downto 0);
+
+	RAM : component er_ram port map(
+		CLK => CLK,
+		RST => RESET,
+		WEN => AUX_WEN,
+		ADDR => AUX_ADDR,
+		DATA => AUX_DATA,
+		REG => INT_REG);
+end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_aux_tb.vhd b/basys3/basys3.srcs/ppu_aux_tb.vhd
new file mode 100644
index 0000000..ab3db62
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_aux_tb.vhd
@@ -0,0 +1,100 @@
+library ieee;
+library unisim;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+use work.ppu_consts.all;
+
+entity ppu_aux_tb is
+end ppu_aux_tb;
+
+architecture behavioral of ppu_aux_tb is
+	component ppu_aux port(
+		CLK : in std_logic; -- system clock
+		RESET : in std_logic; -- reset memory
+
+		-- internal memory block (AUX)
+		AUX_WEN : in std_logic; -- VRAM AUX write enable
+		AUX_ADDR : in std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0); -- VRAM AUX address
+		AUX_DATA : in std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0); -- VRAM AUX data
+		
+		-- aux outputs
+		BG_SHIFT_X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+		BG_SHIFT_Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+		FG_FETCH : out std_logic);
+	end component;
+
+	signal CLK, RST, WEN : std_logic := '0';
+	signal ADDR : std_logic_vector(PPU_AUX_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal DATA : std_logic_vector(PPU_AUX_DATA_WIDTH-1 downto 0) := (others => '0');
+
+	signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+	signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+	signal FG_FETCH : std_logic;
+begin
+	uut : component ppu_aux
+		port map(
+			CLK => CLK,
+			RESET => RST,
+			AUX_WEN => WEN,
+			AUX_ADDR => ADDR,
+			AUX_DATA => DATA,
+			BG_SHIFT_X => BG_SHIFT_X,
+			BG_SHIFT_Y => BG_SHIFT_Y,
+			FG_FETCH => FG_FETCH);
+
+	tb : process
+	begin
+		-- reset
+		RST <= '1';
+		wait for 5 ns;
+		RST <= '0';
+		wait for 5 ns;
+
+		WEN <= '1';
+		-- set BG_SHIFT_X to 178
+		-- set BG_SHIFT_Y to 39
+		-- set FG_FETCH to 1
+		ADDR(0) <= '0';
+		DATA <= x"b327";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		ADDR(0) <= '1';
+		DATA <= x"0002";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		wait for 5 ns;
+
+		-- set BG_SHIFT_X to 30
+		-- set BG_SHIFT_Y to 69
+		-- set FG_FETCH to 0
+		ADDR(0) <= '0';
+		DATA <= x"1e45";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+		ADDR(0) <= '1';
+		DATA <= x"0000";
+
+		CLK <= '1';
+		wait for 1 ns;
+		CLK <= '0';
+		wait for 1 ns;
+
+
+		wait; -- stop for simulator
+	end process;
+end;
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 3e7d46d..ab2ccf1 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -14,7 +14,7 @@ package ppu_consts is
 	constant PPU_FAM_DATA_WIDTH : natural := 16;
 	constant PPU_PAL_ADDR_WIDTH : natural := 6;
 	constant PPU_PAL_DATA_WIDTH : natural := 12;
-	constant PPU_AUX_ADDR_WIDTH : natural := 2;
+	constant PPU_AUX_ADDR_WIDTH : natural := 1;
 	constant PPU_AUX_DATA_WIDTH : natural := 16;
 	constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset
 	constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index a63514c..90e7823 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="15"/>
+    <Option Name="WTXSimLaunchSim" Val="21"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -142,9 +142,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_aux.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="er_ram"/>
+        <Option Name="TopModule" Val="ppu"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -187,9 +193,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_aux_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="er_ram_tb"/>
+        <Option Name="TopModule" Val="ppu_aux_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
-- 
cgit v1.2.3


From 29108f38c5f885412b0a75ae46b85720946cfdb5 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 15:31:12 +0100
Subject: update TMM data width + update memory map (WIP ppu_sprite_bg)

---
 basys3/basys3.srcs/ppu.vhd                         |  4 +-
 basys3/basys3.srcs/ppu_addr_dec.vhd                | 10 ++--
 basys3/basys3.srcs/ppu_consts.vhd                  | 36 +++++++++------
 .../basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci   | 38 ++++++++--------
 basys3/basys3.xpr                                  | 34 +++++++-------
 docs/architecture.md                               | 53 +++++++++++++++-------
 6 files changed, 104 insertions(+), 71 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index acf546f..c798400 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -79,7 +79,7 @@ architecture Behavioral of ppu is
 	end component;
 	component ppu_sprite_bg port( -- background sprite
 		-- inputs
-		CLK : in std_logic; -- system clock
+		CLK : in std_logic; -- pipeline clock
 		RESET : in std_logic; -- reset clock counter
 		OE : in std_logic; -- output enable (of CIDX)
 		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
@@ -100,7 +100,7 @@ architecture Behavioral of ppu is
 	end component;
 	component ppu_sprite_fg port( -- foreground sprite
 		-- inputs
-		CLK : in std_logic; -- system clock
+		CLK : in std_logic; -- pipeline clock
 		RESET : in std_logic; -- reset internal memory and clock counters
 		OE : in std_logic; -- output enable (of CIDX)
 		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
diff --git a/basys3/basys3.srcs/ppu_addr_dec.vhd b/basys3/basys3.srcs/ppu_addr_dec.vhd
index df83964..e0c374f 100644
--- a/basys3/basys3.srcs/ppu_addr_dec.vhd
+++ b/basys3/basys3.srcs/ppu_addr_dec.vhd
@@ -43,9 +43,9 @@ begin
 	AUX_WEN <= AUX_RANGE and WEN;
 
 	-- address ranges
-	TMM_RANGE <= '1' when not (ADDR(15) = '1' and ADDR(14) = '1') else '0';
-	BAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '0') else '0';
-	FAM_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '0') else '0';
-	PAL_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '0') else '0';
-	AUX_RANGE <= '1' when (ADDR(15) = '1' and ADDR(14) = '1') and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '1') else '0';
+	TMM_RANGE <= '1' when not ((ADDR(15) and ADDR(14) and ADDR(13)) or (ADDR(15) and ADDR(14) and ADDR(12))) else '0';
+	BAM_RANGE <= '1' when TMM_RANGE = '0' and (ADDR(11) = '0') else '0';
+	FAM_RANGE <= '1' when TMM_RANGE = '0' and (ADDR(11) = '1' and ADDR(10) = '0') else '0';
+	PAL_RANGE <= '1' when TMM_RANGE = '0' and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '0') else '0';
+	AUX_RANGE <= '1' when TMM_RANGE = '0' and (ADDR(11) = '1' and ADDR(10) = '1' and ADDR(9) = '1') else '0';
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index ab2ccf1..f4d428e 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -1,22 +1,32 @@
+-- https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
 package ppu_consts is
 	constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
 	constant PPU_FG_SPRITE_COUNT : natural := 128; -- amount of foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
-	constant PPU_PALETTE_IDX_WIDTH : natural := 3; -- palette index width (within sprite)
-	constant PPU_PALETTE_WIDTH : natural := 3; -- palette index width (palette table)
-	constant PPU_PALETTE_CIDX_WIDTH : natural := PPU_PALETTE_IDX_WIDTH + PPU_PALETTE_WIDTH; -- global palette index width
-	constant PPU_TMM_ADDR_WIDTH : natural := 16;
-	constant PPU_TMM_DATA_WIDTH : natural := 16;
-	constant PPU_BAM_ADDR_WIDTH : natural := 11;
-	constant PPU_BAM_DATA_WIDTH : natural := 15;
-	constant PPU_FAM_ADDR_WIDTH : natural := 8;
-	constant PPU_FAM_DATA_WIDTH : natural := 16;
-	constant PPU_PAL_ADDR_WIDTH : natural := 6;
-	constant PPU_PAL_DATA_WIDTH : natural := 12;
-	constant PPU_AUX_ADDR_WIDTH : natural := 1;
-	constant PPU_AUX_DATA_WIDTH : natural := 16;
+	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
+	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
+	constant PPU_PALETTE_CIDX_WIDTH : natural := PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH; -- global palette index width
+	constant PPU_TMM_ADDR_WIDTH : natural := 16; -- tilemap memory ram bus address width
+	constant PPU_TMM_DATA_WIDTH : natural := 15; -- tilemap memory ram bus data width
+	constant PPU_BAM_ADDR_WIDTH : natural := 11; -- background attribute memory ram bus address width
+	constant PPU_BAM_DATA_WIDTH : natural := 15; -- background attribute memory ram bus data width
+	constant PPU_FAM_ADDR_WIDTH : natural := 8; -- foreground attribute memory ram bus address width
+	constant PPU_FAM_DATA_WIDTH : natural := 16; -- foreground attribute memory ram bus data width
+	constant PPU_PAL_ADDR_WIDTH : natural := 6; -- palette memory ram bus address width
+	constant PPU_PAL_DATA_WIDTH : natural := 12; -- palette memory ram bus data width
+	constant PPU_AUX_ADDR_WIDTH : natural := 1; -- auxiliary memory ram bus address width
+	constant PPU_AUX_DATA_WIDTH : natural := 16; -- auxiliary memory ram bus data width
 	constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset
 	constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset
+	constant PPU_SPRITE_WIDTH : natural := 16; -- sprite width (pixels)
+	constant PPU_SPRITE_HEIGHT : natural := 16; -- sprite height (pixels)
+	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (pixels)
+	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (pixels)
+	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- amount of tiles (horizontally) on background canvas
+	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- amount of tiles (vertically) on background canvas
+	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- amount of bits needed to index a tile from TMM memory
+	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- amount of pixels defined in one word in TMM memory
+	constant PPU_TILE_SIZE : natural := 48;
 end package ppu_consts;
 
diff --git a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
index 24d2b58..9663635 100644
--- a/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
+++ b/basys3/basys3.srcs/sources_1/ip/ppu_tmm/ppu_tmm.xci
@@ -14,7 +14,7 @@
         "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ],
-        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -32,13 +32,13 @@
         "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
         "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "Write_Width_A": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Write_Depth_A": [ { "value": "49152", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "Read_Width_A": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_A": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "53248", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "15", "resolve_type": "user", "usage": "all" } ],
         "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
         "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
-        "Write_Width_B": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "Read_Width_B": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "15", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -110,10 +110,10 @@
         "C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
-        "C_WRITE_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_READ_WIDTH_A": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_DEPTH_A": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_READ_DEPTH_A": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
@@ -124,10 +124,10 @@
         "C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
-        "C_WRITE_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_READ_WIDTH_B": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_WRITE_DEPTH_B": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_READ_DEPTH_B": [ { "value": "49152", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "53248", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ADDRB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -153,9 +153,9 @@
         "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_COUNT_36K_BRAM": [ { "value": "22", "resolve_type": "generated", "usage": "all" } ],
-        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
-        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     16.534446 mW", "resolve_type": "generated", "usage": "all" } ]
+        "C_COUNT_36K_BRAM": [ { "value": "19", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     13.861152 mW", "resolve_type": "generated", "usage": "all" } ]
       },
       "project_parameters": {
         "ARCHITECTURE": [ { "value": "artix7" } ],
@@ -189,8 +189,8 @@
         "rsta": [ { "direction": "in", "driver_value": "0" } ],
         "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "addra": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
-        "dina": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
-        "douta": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
+        "douta": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
         "rsta_busy": [ { "direction": "out" } ]
       },
       "interfaces": {
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 90e7823..8dcc698 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,20 +61,20 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="21"/>
+    <Option Name="WTXSimLaunchSim" Val="27"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="3"/>
-    <Option Name="WTModelSimExportSim" Val="3"/>
-    <Option Name="WTQuestaExportSim" Val="3"/>
+    <Option Name="WTXSimExportSim" Val="4"/>
+    <Option Name="WTModelSimExportSim" Val="4"/>
+    <Option Name="WTQuestaExportSim" Val="4"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="3"/>
-    <Option Name="WTRivieraExportSim" Val="3"/>
-    <Option Name="WTActivehdlExportSim" Val="3"/>
+    <Option Name="WTVcsExportSim" Val="4"/>
+    <Option Name="WTRivieraExportSim" Val="4"/>
+    <Option Name="WTActivehdlExportSim" Val="4"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -148,9 +148,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_bg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu"/>
+        <Option Name="TopModule" Val="ppu_sprite_bg"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -163,7 +169,7 @@
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/ppu_addr_dec_tb.vhd">
-        <FileInfo SFType="VHDL2008">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -201,7 +207,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_aux_tb"/>
+        <Option Name="TopModule" Val="ppu_addr_dec_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -270,9 +276,7 @@
   <Runs Version="1" Minor="19">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
@@ -301,9 +305,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/docs/architecture.md b/docs/architecture.md
index a60e0da..56bbb62 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -227,16 +227,17 @@ Important notes:
 - The PPU's memory bus has 16-bit addresses and 16-bit words.
 - Some memory regions use physical word sizes smaller than 16-bits, so
   "unneeded" bits will be discarded by the PPU.
-- All "fields" or words containing multiple bit strings representing different
-  pieces of information are ordered from MSB to LSB.
+- Apparent size means the amount of addresses in a given memory region. As
+  mentioned earlier, the exact word sizes of a memory area can vary, though
+  this is not visible to the CPU as all data is presented as 16-bit words.
 
-|Address offset|Size (16-bit words)|Alias|Description|
+|Address offset|Apparent size|Alias|Description|
 |-|-|-|-|
-|`0x0000`|`0xc000`|TMM  |[tilemap memory][TMM]|
-|`0xc000`|`0x04b0`|BAM  |[background attribute memory][BAM]|
-|`0xc800`|`0x0100`|FAM  |[foreground attribute memory][FAM]|
-|`0xcc00`|`0x0040`|PAL  |[palettes][PAL]|
-|`0xce00`|`0x0002`|AUX  |[auxiliary memory][AUX]|
+|`0x0000`|`0xd000`|TMM  |[tilemap memory][TMM]|
+|`0xd000`|`0x04b0`|BAM  |[background attribute memory][BAM]|
+|`0xd800`|`0x0100`|FAM  |[foreground attribute memory][FAM]|
+|`0xdc00`|`0x0040`|PAL  |[palettes][PAL]|
+|`0xde00`|`0x0002`|AUX  |[auxiliary memory][AUX]|
 
 This table contains the "official" PPU register offsets and sizes. Due to the
 way the address decoder works, some of these memory regions might be duplicated
@@ -247,24 +248,44 @@ there is no address validity checking.
 [TMM]: #tilemap-memory
 ### Tilemap memory
 
-- Each sprite takes up 768 bits spread across 48 16-bit words
-- Sprites and pixels are stored adjacently in memory without padding
-- Pixel order is from top-left to bottom-right in (English) reading order.
+- Each sprite takes up 768 bits spread across 52 15-bit words (with one
+  discarded padding bit per word)
+- Pixel index order is from top-left to bottom-right in (English) reading
+  order.
+- Bits `14 downto 3` of the byte with the highest address for a given tile are
+  not used
+- To calculate TMM address $a$ for any given pixel $p$ of tile with index $t$,
+  compute $a=52*t+\left\lfloor\frac{p}{5}\right\rfloor$
+
+Word format:
+
+|Range (VHDL)|Description|
+|-|-|
+|`15`|(discarded)|
+|`14 downto 12`|pixel $n+4$|
+|`11 downto 9`|pixel $n+3$|
+|`8 downto 6`|pixel $n+2$|
+|`5 downto 3`|pixel $n+1$|
+|`2 downto 0`|pixel $n+0$|
+
 
 [BAM]: #background-attribute-memory
 ### Background attribute memory
 
 - 15-bit words (MSB discarded in hardware)
-- Address indicates which background sprite is currently targeted in reading order  
-  e.g. $\textrm{addr} = c000_{\textrm{hex}} + x + y*w$ where $x$ and $y$ are the background tile, and $w$ is the amount of horizontal tiles fit on the background layer (40)
+- Address indicates which background sprite is currently targeted in reading
+  order  
+  e.g. $\textrm{addr} = c000_{\textrm{hex}} + x + y*w$ where $x$ and $y$
+  are the background tile, and $w$ is the amount of horizontal tiles fit on the
+  background layer (40)
 
 Word format:
 
 |Range (VHDL)|Description|
 |-|-|
-|`15`|Flip horizontally|
-|`14`|Flip vertically|
-|`13`|(unused)|
+|`15`|(discarded)|
+|`14`|Flip horizontally|
+|`13`|Flip vertically|
 |`12 downto 10`|Palette index for tile|
 |`9 downto 0`|Tilemap index|
 
-- 
cgit v1.2.3


From 27b39499095ccb7e7e73a78776946b60fc96fb05 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 17:13:06 +0100
Subject: PPU background sprite component done (but unverified)

---
 basys3/basys3.srcs/ppu_consts.vhd           |   4 +-
 basys3/basys3.srcs/ppu_sprite_bg.vhd        | 150 ++++++++++++++++++++++++++++
 basys3/basys3.srcs/ppu_sprite_bg_tb.vhd     |  86 ++++++++++++++++
 basys3/basys3.srcs/ppu_sprite_transform.vhd |  24 +++++
 basys3/basys3.xpr                           |  16 ++-
 5 files changed, 277 insertions(+), 3 deletions(-)
 create mode 100644 basys3/basys3.srcs/ppu_sprite_bg.vhd
 create mode 100644 basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
 create mode 100644 basys3/basys3.srcs/ppu_sprite_transform.vhd

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index f4d428e..89b7a7a 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -21,12 +21,14 @@ package ppu_consts is
 	constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset
 	constant PPU_SPRITE_WIDTH : natural := 16; -- sprite width (pixels)
 	constant PPU_SPRITE_HEIGHT : natural := 16; -- sprite height (pixels)
+	constant PPU_SPRITE_POS_H_WIDTH: natural := 4; -- bits needed to identify horizontal pixel within sprite
+	constant PPU_SPRITE_POS_V_WIDTH: natural := 4; -- bits needed to identify vertical pixel within sprite
 	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (pixels)
 	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (pixels)
 	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- amount of tiles (horizontally) on background canvas
 	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- amount of tiles (vertically) on background canvas
 	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- amount of bits needed to index a tile from TMM memory
 	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- amount of pixels defined in one word in TMM memory
-	constant PPU_TILE_SIZE : natural := 48;
+	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- amount of words needed for a single sprite
 end package ppu_consts;
 
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
new file mode 100644
index 0000000..a92c401
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -0,0 +1,150 @@
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity ppu_sprite_bg is port(
+	-- inputs
+	CLK : in std_logic; -- pipeline clock
+	RESET : in std_logic; -- reset clock counter
+	OE : in std_logic; -- output enable (of CIDX)
+	X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+	Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+	
+	-- aux inputs
+	BG_SHIFT_X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+	BG_SHIFT_Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+
+	-- used memory blocks
+	BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	BAM_DATA : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+	TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+	-- outputs
+	CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color
+end ppu_sprite_bg;
+
+architecture Behavioral of ppu_sprite_bg is
+	component ppu_sprite_transform port(
+		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		FLIP_H, FLIP_V : in std_logic; -- flip sprite
+		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+	end component;
+
+	signal O_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal I_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+	signal O_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal I_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+	signal FLIP_H, FLIP_V : std_logic := '0';
+	signal TMM_IDX : std_logic_vector(PPU_TILE_INDEX_WIDTH-1 downto 0) := (others => '0');
+
+	alias BAM_DATA_COL_IDX is I_BAM_DATA(12 downto 10);
+	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0);
+	signal O_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');
+
+	type states is (PL_BAM_ADDR, PL_BAM_DATA, PL_TMM_ADDR, PL_TMM_DATA);
+	signal state, next_state : states := PL_BAM_ADDR;
+
+	-- docs/architecture.md#background-attribute-memory
+	alias BAM_DATA_FLIP_H is I_BAM_DATA(14);
+	alias BAM_DATA_FLIP_V is I_BAM_DATA(13);
+	alias BAM_DATA_TILE_IDX is I_BAM_DATA(9 downto 0);
+
+	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
+	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
+	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile
+	signal TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile
+	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
+	signal TILEMAP_WORD_OFFSET : integer := 0;
+	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal PIXEL_BIT_OFFSET : integer := 0;
+begin
+	-- CIDX tri-state driver
+	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
+
+	-- internal line separators
+	FLIP_H <= BAM_DATA_FLIP_H;
+	FLIP_V <= BAM_DATA_FLIP_V;
+	O_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
+
+	-- BAM ADDR
+	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
+	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
+	TILE_IDX_X <= PIXEL_ABS_X / 16;
+	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
+	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
+	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
+	O_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
+
+	-- BAM DATA + FAM ADDR
+	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
+	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
+	transform: component ppu_sprite_transform port map(
+		XI => TRANSFORM_XI,
+		YI => TRANSFORM_YI,
+		FLIP_H => FLIP_H,
+		FLIP_V => FLIP_V,
+		XO => TRANSFORM_XO,
+		YO => TRANSFORM_YO);
+	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
+	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
+
+	TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
+	TILEMAP_WORD_OFFSET <= TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
+	PIXEL_BIT_OFFSET <= TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
+
+	O_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+
+	-- TMM DATA
+	with PIXEL_BIT_OFFSET select
+		TMM_DATA_PAL_IDX <= TMM_DATA(2 downto 0) when 0,
+		                    TMM_DATA(5 downto 3) when 1,
+		                    TMM_DATA(8 downto 6) when 2,
+		                    TMM_DATA(11 downto 9) when 3,
+		                    TMM_DATA(14 downto 12) when 4,
+		                    (others => '0') when others;
+
+	-- state machine (pipeline stage counter)
+	fsm: process(CLK, RESET)
+	begin
+		if RESET = '1' then
+			state <= PL_BAM_ADDR;
+		elsif rising_edge(CLK) then
+			state <= next_state;
+		end if;
+	end process;
+
+	-- sync read/write
+	process(state)
+	begin
+		next_state <= state;
+		case state is
+			when PL_BAM_ADDR =>
+				next_state <= PL_BAM_DATA;
+				BAM_ADDR <= O_BAM_ADDR;
+
+			when PL_BAM_DATA =>
+				next_state <= PL_TMM_ADDR;
+				I_BAM_DATA <= BAM_DATA;
+				
+			when PL_TMM_ADDR =>
+				next_state <= PL_TMM_DATA;
+				TMM_ADDR <= O_TMM_ADDR;
+
+			when PL_TMM_DATA =>
+				next_state <= PL_BAM_ADDR;
+				I_TMM_DATA <= TMM_DATA;
+
+				
+		end case;
+	end process;
+
+end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
new file mode 100644
index 0000000..2dee2fe
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
@@ -0,0 +1,86 @@
+library ieee;
+library work;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+use work.ppu_consts.all;
+
+entity ppu_sprite_bg_tb is
+end ppu_sprite_bg_tb;
+
+architecture Behavioral of ppu_sprite_bg_tb is
+	component ppu_sprite_bg port(
+		-- inputs
+		CLK : in std_logic; -- pipeline clock
+		RESET : in std_logic; -- reset clock counter
+		OE : in std_logic; -- output enable (of CIDX)
+		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+		
+		-- aux inputs
+		BG_SHIFT_X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+		BG_SHIFT_Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+
+		-- used memory blocks
+		BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+		BAM_DATA : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+		TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+		TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+		-- outputs
+		CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color
+	end component;
+	signal CLK : std_logic := '0'; -- pipeline clock
+	signal RESET : std_logic := '0'; -- reset clock counter
+	signal OE : std_logic := '0'; -- output enable (of CIDX)
+	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0'); -- current screen pixel x
+	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0'); -- current screen pixel y
+	signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
+	signal BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	signal BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	signal TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color
+begin
+	uut : ppu_sprite_bg port map(
+		CLK => CLK,
+		RESET => RESET,
+		OE => OE,
+		X => X,
+		Y => Y,
+		BG_SHIFT_X => BG_SHIFT_X,
+		BG_SHIFT_Y => BG_SHIFT_Y,
+		BAM_ADDR => BAM_ADDR,
+		BAM_DATA => BAM_DATA,
+		TMM_ADDR => TMM_ADDR,
+		TMM_DATA => TMM_DATA,
+		CIDX => CIDX);
+
+	BAM_DATA <= std_logic_vector(to_unsigned(16#4814#, PPU_BAM_DATA_WIDTH));  -- hex((1 << 14) | (0 << 13) | (2 << 10) | (20 << 0))
+	TMM_DATA <= std_logic_vector(to_unsigned(16#ffff#, PPU_TMM_DATA_WIDTH));
+	X <= std_logic_vector(to_unsigned(25, PPU_POS_H_WIDTH));
+	Y <= std_logic_vector(to_unsigned(60, PPU_POS_V_WIDTH));
+	BG_SHIFT_X <= std_logic_vector(to_unsigned(3, PPU_POS_H_WIDTH));
+	BG_SHIFT_Y <= std_logic_vector(to_unsigned(3, PPU_POS_V_WIDTH));
+
+	tb : process
+	begin
+		for i in 0 to 32 loop
+			if i > 10 then
+				OE <= '1';
+			end if;
+			if i > 20 then
+				RESET <= '1';
+			end if;
+	
+			wait for 5 ns;
+			CLK <= '1';
+			wait for 5 ns;
+			CLK <= '0';
+		end loop;
+		wait; -- stop for simulator
+	end process;
+end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_sprite_transform.vhd b/basys3/basys3.srcs/ppu_sprite_transform.vhd
new file mode 100644
index 0000000..d1b1a23
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_transform.vhd
@@ -0,0 +1,24 @@
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity ppu_sprite_transform is port( -- flip sprites
+	XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+	YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+	FLIP_H, FLIP_V : in std_logic; -- flip sprite
+	XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+	YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+end ppu_sprite_transform;
+
+architecture Behavioral of ppu_sprite_transform is
+	signal FLIPPED_X : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal FLIPPED_Y : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+begin
+	FLIPPED_X <= std_logic_vector(to_unsigned(PPU_SPRITE_WIDTH-1 - to_integer(unsigned(XI)), PPU_SPRITE_POS_H_WIDTH));
+	FLIPPED_Y <= std_logic_vector(to_unsigned(PPU_SPRITE_HEIGHT-1 - to_integer(unsigned(YI)), PPU_SPRITE_POS_V_WIDTH));
+
+	XO <= FLIPPED_X when FLIP_H = '1' else XI;
+	YO <= FLIPPED_Y when FLIP_V = '1' else YI;
+end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 8dcc698..556c73e 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="27"/>
+    <Option Name="WTXSimLaunchSim" Val="31"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -154,6 +154,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_transform.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="ppu_sprite_bg"/>
@@ -205,9 +211,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_bg_tb.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_addr_dec_tb"/>
+        <Option Name="TopModule" Val="ppu_sprite_bg_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
-- 
cgit v1.2.3


From 55c3e36b2367daf6b9b3f894fb6a65b6d6b18158 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 14:21:33 +0100
Subject: PPU debugged and working (but with unwanted latches)

---
 basys3/basys3.srcs/ppu_sprite_bg.vhd    | 20 +++++++++++++++-----
 basys3/basys3.srcs/ppu_sprite_bg_tb.vhd | 25 +++++++++++++++++++++++--
 basys3/basys3.xpr                       |  8 +++++++-
 3 files changed, 45 insertions(+), 8 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index a92c401..391083f 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -67,6 +67,8 @@ architecture Behavioral of ppu_sprite_bg is
 	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 	signal PIXEL_BIT_OFFSET : integer := 0;
 begin
+	-- TODO: fix latches
+
 	-- CIDX tri-state driver
 	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
 
@@ -105,18 +107,26 @@ begin
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= TMM_DATA(2 downto 0) when 0,
-		                    TMM_DATA(5 downto 3) when 1,
-		                    TMM_DATA(8 downto 6) when 2,
-		                    TMM_DATA(11 downto 9) when 3,
-		                    TMM_DATA(14 downto 12) when 4,
+		TMM_DATA_PAL_IDX <= I_TMM_DATA(2 downto 0) when 0,
+		                    I_TMM_DATA(5 downto 3) when 1,
+		                    I_TMM_DATA(8 downto 6) when 2,
+		                    I_TMM_DATA(11 downto 9) when 3,
+		                    I_TMM_DATA(14 downto 12) when 4,
 		                    (others => '0') when others;
 
 	-- state machine (pipeline stage counter)
 	fsm: process(CLK, RESET)
 	begin
 		if RESET = '1' then
+			-- reset state
 			state <= PL_BAM_ADDR;
+			-- reset internal pipeline registers
+			-- O_BAM_ADDR <= (others => '0');
+			-- I_BAM_DATA <= (others => '0');
+			-- O_TMM_ADDR <= (others => '0');
+			-- I_TMM_DATA <= (others => '0');
+			-- reset working color register
+			-- O_CIDX <= (others => '0');
 		elsif rising_edge(CLK) then
 			state <= next_state;
 		end if;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
index 2dee2fe..65da15c 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
@@ -59,13 +59,34 @@ begin
 		TMM_DATA => TMM_DATA,
 		CIDX => CIDX);
 
-	BAM_DATA <= std_logic_vector(to_unsigned(16#4814#, PPU_BAM_DATA_WIDTH));  -- hex((1 << 14) | (0 << 13) | (2 << 10) | (20 << 0))
-	TMM_DATA <= std_logic_vector(to_unsigned(16#ffff#, PPU_TMM_DATA_WIDTH));
+	-- inputs
+	-- BAM_DATA -> FLIP_H + palette index 2 + tilemap index 10
+	-- TMM_DATA -> all pixels color 7
+	-- X -> 25
+	-- Y -> 60
+	-- BG_SHIFT_X -> 3
+	-- BG_SHIFT_Y -> 3
+	BAM_DATA <= 15x"4814"; -- hex((1 << 14) | (0 << 13) | (2 << 10) | (20 << 0))
+	TMM_DATA <= 15x"7e3f"; -- hex(0x7fff & ~(0b111 << 6))
 	X <= std_logic_vector(to_unsigned(25, PPU_POS_H_WIDTH));
 	Y <= std_logic_vector(to_unsigned(60, PPU_POS_V_WIDTH));
 	BG_SHIFT_X <= std_logic_vector(to_unsigned(3, PPU_POS_H_WIDTH));
 	BG_SHIFT_Y <= std_logic_vector(to_unsigned(3, PPU_POS_V_WIDTH));
 
+	-- expected outputs:
+	-- absolute pixel coordinates -> (28, 63)
+	-- absolute background canvas tile index coordinates -> (1, 3)
+	-- tile index -> 3 * 40 + 1 = 121
+	-- BAM_ADDR => 121 (OK)
+	-- sprite local coordinates -> (12, 15)
+	-- transformed local coordinates -> (12, 0) (apply FLIP_H)
+	-- pixel index -> 0 * 16 + 12 = 12
+	-- pixel word address -> 52 * 20 + 12//5 -> 1042
+	-- TMM_ADDR => 1042 (OK)
+	-- pixel bits -> [pixel n+] = 12 % 5 = 2 -> 8 downto 6
+	-- cidx should be -- (2 << 3) | (0 << 0) = 16
+	-- CIDX => 16 (OK)
+
 	tb : process
 	begin
 		for i in 0 to 32 loop
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 556c73e..c79fd58 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="31"/>
+    <Option Name="WTXSimLaunchSim" Val="39"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -217,6 +217,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_transform_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="ppu_sprite_bg_tb"/>
-- 
cgit v1.2.3


From 9ab2a3d4b4304a4f489e100a6b66d6ee414143e7 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 15:32:11 +0100
Subject: background sprite component done, tested, and working without latches

---
 basys3/basys3.srcs/ppu_sprite_bg.vhd | 144 ++++++++++++++++-------------------
 basys3/basys3.xpr                    |  13 +++-
 2 files changed, 75 insertions(+), 82 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 391083f..d8235f5 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -6,6 +6,7 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use work.ppu_consts.all;
 
+-- TODO: add input stable / output stable pipeline stages if this doesn't work with propagation delays
 entity ppu_sprite_bg is port(
 	-- inputs
 	CLK : in std_logic; -- pipeline clock
@@ -37,124 +38,107 @@ architecture Behavioral of ppu_sprite_bg is
 		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
-	signal O_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal I_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
-	signal O_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal I_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
-
-	signal FLIP_H, FLIP_V : std_logic := '0';
-	signal TMM_IDX : std_logic_vector(PPU_TILE_INDEX_WIDTH-1 downto 0) := (others => '0');
-
-	alias BAM_DATA_COL_IDX is I_BAM_DATA(12 downto 10);
-	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0);
-	signal O_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');
+	-- BAM and TMM in/out temp + registers
+	signal T_BAM_ADDR, R_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_BAM_DATA, R_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_ADDR, R_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_DATA, R_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
 
+	-- state machine for synchronizing pipeline stages
 	type states is (PL_BAM_ADDR, PL_BAM_DATA, PL_TMM_ADDR, PL_TMM_DATA);
-	signal state, next_state : states := PL_BAM_ADDR;
+	signal state : states := PL_BAM_ADDR;
 
 	-- docs/architecture.md#background-attribute-memory
-	alias BAM_DATA_FLIP_H is I_BAM_DATA(14);
-	alias BAM_DATA_FLIP_V is I_BAM_DATA(13);
-	alias BAM_DATA_TILE_IDX is I_BAM_DATA(9 downto 0);
+	alias BAM_DATA_FLIP_H is R_BAM_DATA(14); -- flip horizontally
+	alias BAM_DATA_FLIP_V is R_BAM_DATA(13); -- flip vertically
+	alias BAM_DATA_TILE_IDX is R_BAM_DATA(9 downto 0); -- tilemap tile index
+	alias BAM_DATA_COL_IDX is R_BAM_DATA(12 downto 10); -- palette for sprite
 
+	-- auxiliary signals (temp variables)
 	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
 	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile
-	signal TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile
+	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
 	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	signal TILEMAP_WORD_OFFSET : integer := 0;
-	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
-	signal PIXEL_BIT_OFFSET : integer := 0;
+	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
+	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
+	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
+	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
+	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
+	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
+	signal T_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- output color buffer/register
 begin
-	-- TODO: fix latches
-
-	-- CIDX tri-state driver
-	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
-
-	-- internal line separators
-	FLIP_H <= BAM_DATA_FLIP_H;
-	FLIP_V <= BAM_DATA_FLIP_V;
-	O_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
-
-	-- BAM ADDR
+	-- output drivers
+	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
+	BAM_ADDR <= R_BAM_ADDR;
+	TMM_ADDR <= R_TMM_ADDR;
+	T_BAM_DATA <= BAM_DATA;
+	T_TMM_DATA <= TMM_DATA;
+	-- CIDX combination
+	T_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
+
+	-- BAM address calculations
 	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
 	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
 	TILE_IDX_X <= PIXEL_ABS_X / 16;
 	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
 	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
 	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
-	O_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
+	T_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
 
-	-- BAM DATA + FAM ADDR
+	-- BAM data dependant calculations
 	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
 	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
 	transform: component ppu_sprite_transform port map(
 		XI => TRANSFORM_XI,
 		YI => TRANSFORM_YI,
-		FLIP_H => FLIP_H,
-		FLIP_V => FLIP_V,
+		FLIP_H => BAM_DATA_FLIP_H,
+		FLIP_V => BAM_DATA_FLIP_V,
 		XO => TRANSFORM_XO,
 		YO => TRANSFORM_YO);
 	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
 	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
 
-	TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	TILEMAP_WORD_OFFSET <= TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	PIXEL_BIT_OFFSET <= TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
 
-	O_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= I_TMM_DATA(2 downto 0) when 0,
-		                    I_TMM_DATA(5 downto 3) when 1,
-		                    I_TMM_DATA(8 downto 6) when 2,
-		                    I_TMM_DATA(11 downto 9) when 3,
-		                    I_TMM_DATA(14 downto 12) when 4,
+		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
+		                    R_TMM_DATA(5 downto 3) when 1,
+		                    R_TMM_DATA(8 downto 6) when 2,
+		                    R_TMM_DATA(11 downto 9) when 3,
+		                    R_TMM_DATA(14 downto 12) when 4,
 		                    (others => '0') when others;
 
-	-- state machine (pipeline stage counter)
-	fsm: process(CLK, RESET)
+	-- state machine (pipeline stage counter) + sync r/w
+	process(CLK, RESET)
 	begin
 		if RESET = '1' then
 			-- reset state
 			state <= PL_BAM_ADDR;
 			-- reset internal pipeline registers
-			-- O_BAM_ADDR <= (others => '0');
-			-- I_BAM_DATA <= (others => '0');
-			-- O_TMM_ADDR <= (others => '0');
-			-- I_TMM_DATA <= (others => '0');
-			-- reset working color register
-			-- O_CIDX <= (others => '0');
+			R_BAM_ADDR <= (others => '0');
+			R_BAM_DATA <= (others => '0');
+			R_TMM_ADDR <= (others => '0');
+			R_TMM_DATA <= (others => '0');
 		elsif rising_edge(CLK) then
-			state <= next_state;
+			case state is
+				when PL_BAM_ADDR =>
+					state <= PL_BAM_DATA;
+					R_BAM_ADDR <= T_BAM_ADDR;
+				when PL_BAM_DATA =>
+					state <= PL_TMM_ADDR;
+					R_BAM_DATA <= T_BAM_DATA;
+				when PL_TMM_ADDR =>
+					state <= PL_TMM_DATA;
+					R_TMM_ADDR <= T_TMM_ADDR;
+				when PL_TMM_DATA =>
+					state <= PL_BAM_ADDR;
+					R_TMM_DATA <= T_TMM_DATA;
+			end case;
 		end if;
 	end process;
-
-	-- sync read/write
-	process(state)
-	begin
-		next_state <= state;
-		case state is
-			when PL_BAM_ADDR =>
-				next_state <= PL_BAM_DATA;
-				BAM_ADDR <= O_BAM_ADDR;
-
-			when PL_BAM_DATA =>
-				next_state <= PL_TMM_ADDR;
-				I_BAM_DATA <= BAM_DATA;
-				
-			when PL_TMM_ADDR =>
-				next_state <= PL_TMM_DATA;
-				TMM_ADDR <= O_TMM_ADDR;
-
-			when PL_TMM_DATA =>
-				next_state <= PL_BAM_ADDR;
-				I_TMM_DATA <= TMM_DATA;
-
-				
-		end case;
-	end process;
-
 end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index c79fd58..af6fbe7 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="39"/>
+    <Option Name="WTXSimLaunchSim" Val="42"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -239,6 +239,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -292,11 +300,12 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
-- 
cgit v1.2.3


From 3bb4bbb64bfc9263520b68cac5b3c6caaa37d19d Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 16:40:08 +0100
Subject: WIP ppu foreground sprite component

---
 basys3/basys3.srcs/er_ram.vhd           |   8 +-
 basys3/basys3.srcs/ppu.vhd              |  70 +++++++-------
 basys3/basys3.srcs/ppu_sprite_fg.vhd    | 164 ++++++++++++++++++++++++++++++++
 basys3/basys3.srcs/ppu_sprite_fg_tb.vhd |  15 +++
 basys3/basys3.xpr                       |  16 +++-
 docs/architecture.md                    |   6 ++
 6 files changed, 241 insertions(+), 38 deletions(-)
 create mode 100644 basys3/basys3.srcs/ppu_sprite_fg.vhd
 create mode 100644 basys3/basys3.srcs/ppu_sprite_fg_tb.vhd

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd
index f106d4e..66f905b 100644
--- a/basys3/basys3.srcs/er_ram.vhd
+++ b/basys3/basys3.srcs/er_ram.vhd
@@ -21,8 +21,8 @@ end er_ram;
 architecture Behavioral of er_ram is
 	component er_ram_mod
 		generic(
-			W : natural := 1; -- module data width
-			ADDR_W : natural := 1; -- address width
+			W : natural := DATA_W; -- module data width
+			ADDR_W : natural := ADDR_W; -- address width
 			ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match
 		port(
 			CLK : in std_logic; -- clock
@@ -36,12 +36,12 @@ architecture Behavioral of er_ram is
 begin
 	REG <= INT_REG;
 
-	registers : for idx in ADDR_LOW to ADDR_LOW + ADDR_RANGE - 1 generate
+	registers : for idx in 0 to ADDR_RANGE - 1 generate
 		reg : component er_ram_mod
 			generic map(
 				W => DATA_W,
 				ADDR_W => ADDR_W,
-				ADDR_M => std_logic_vector(to_unsigned(idx, ADDR_W)))
+				ADDR_M => std_logic_vector(to_unsigned(ADDR_LOW + idx, ADDR_W)))
 			port map(
 				CLK => CLK,
 				RST => RST,
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index c798400..22ee210 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -18,6 +18,7 @@ entity ppu is port(
 end ppu;
 
 architecture Behavioral of ppu is
+	-- TODO: separate SPRITE_BG and SPRITE_FG lines (foreground_sprite only needs 2 clock cycles)
 	component ppu_pceg port( -- pipeline clock edge generator
 		CLK : in std_logic; -- system clock
 		RESET : in std_logic; -- async reset
@@ -98,27 +99,30 @@ architecture Behavioral of ppu is
 		-- outputs
 		CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color
 	end component;
-	component ppu_sprite_fg port( -- foreground sprite
-		-- inputs
-		CLK : in std_logic; -- pipeline clock
-		RESET : in std_logic; -- reset internal memory and clock counters
-		OE : in std_logic; -- output enable (of CIDX)
-		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index)
+	component ppu_sprite_fg -- foreground sprite
+		generic (
+			IDX : natural := 0);
+		port(
+			-- inputs
+			CLK : in std_logic; -- pipeline clock
+			RESET : in std_logic; -- reset internal memory and clock counters
+			OE : in std_logic; -- output enable (of CIDX)
+			X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+			Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+			FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index)
 
-		-- internal memory block (FAM)
-		FAM_WEN : in std_logic; -- VRAM FAM write enable
-		FAM_ADDR : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address
-		FAM_DATA : in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data
+			-- internal memory block (FAM)
+			FAM_WEN : in std_logic; -- VRAM FAM write enable
+			FAM_ADDR : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address
+			FAM_DATA : in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data
 
-		-- used memory blocks
-		TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
-		TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+			-- used memory blocks
+			TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+			TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
 
-		-- outputs
-		CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color
-		HIT : out std_logic); -- current pixel is not transparent
+			-- outputs
+			CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color
+			HIT : out std_logic); -- current pixel is not transparent
 	end component;
 	component ppu_comp port( -- compositor
 		FG_HIT : in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
@@ -266,20 +270,22 @@ begin
 		CIDX => CIDX);
 
 	foreground_sprites : for FG_IDX in 0 to PPU_FG_SPRITE_COUNT-1 generate
-		foreground_sprite : component ppu_sprite_fg port map(
-			CLK => PL_SPRITE,
-			RESET => SYSRST,
-			OE => FG_EN(FG_IDX),
-			X => X,
-			Y => Y,
-			FETCH => FG_FETCH,
-			FAM_WEN => FAM_WEN,
-			FAM_ADDR => FAM_AO,
-			FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
-			TMM_ADDR => TMM_AI,
-			TMM_DATA => TMM_DO,
-			CIDX => CIDX,
-			HIT => FG_HIT(FG_IDX));
+		foreground_sprite : component ppu_sprite_fg
+			generic map( IDX => FG_IDX )
+			port map(
+				CLK => PL_SPRITE,
+				RESET => SYSRST,
+				OE => FG_EN(FG_IDX),
+				X => X,
+				Y => Y,
+				FETCH => FG_FETCH,
+				FAM_WEN => FAM_WEN,
+				FAM_ADDR => FAM_AO,
+				FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
+				TMM_ADDR => TMM_AI,
+				TMM_DATA => TMM_DO,
+				CIDX => CIDX,
+				HIT => FG_HIT(FG_IDX));
 	end generate;
 
 	compositor : component ppu_comp port map( -- compositor
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
new file mode 100644
index 0000000..340104a
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -0,0 +1,164 @@
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+-- TODO: add input stable / output stable pipeline stages if this doesn't work with propagation delays
+entity ppu_sprite_fg is -- foreground sprite
+	generic (
+		IDX : natural := 0); -- sprite index number
+	port(
+		-- inputs
+		CLK : in std_logic; -- system clock
+		PL_CLK : in std_logic; -- pipeline clock
+		RESET : in std_logic; -- reset internal memory and clock counters
+		OE : in std_logic; -- output enable (of CIDX)
+		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+		FETCH : in std_logic; -- fetch sprite data from TMM
+
+		-- internal memory block (FAM)
+		FAM_WEN : in std_logic; -- VRAM FAM write enable
+		FAM_ADDR : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address
+		FAM_DATA : in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data
+
+		-- used memory blocks
+		TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+		TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+		-- outputs
+		CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color
+		HIT : out std_logic); -- current pixel is not transparent
+end ppu_sprite_fg;
+
+architecture Behavioral of ppu_sprite_fg is
+	component ppu_sprite_transform port(
+		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		FLIP_H, FLIP_V : in std_logic; -- flip sprite
+		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+	end component;
+	component er_ram -- exposed register RAM
+		generic(
+			ADDR_W : natural := PPU_FAM_ADDR_WIDTH; -- ADDR line width
+			DATA_W : natural := PPU_FAM_DATA_WIDTH; -- DATA line width
+			ADDR_LOW : natural := IDX*2; -- starting address
+			ADDR_RANGE : natural := 2); -- amount of valid addresses after ADDR_LOW
+		port(
+			CLK : in std_logic; -- clock
+			RST : in std_logic; -- async memory clear
+			WEN : in std_logic; -- write enable
+			ADDR : in std_logic_vector(ADDR_W-1 downto 0); -- address line
+			DATA : in std_logic_vector(DATA_W-1 downto 0); -- data input
+			REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output
+	end component;
+
+	-- FAM and TMM in/out temp + registers
+	signal T_TMM_ADDR, R_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_DATA, R_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
+
+	-- state machine for synchronizing pipeline stages
+	type states is (PL_TMM_ADDR, PL_TMM_DATA);
+	signal state : states := PL_TMM_ADDR;
+
+	-- auxiliary signals (temp variables)
+	signal T_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- output color buffer/register
+	signal INT_FAM : std_logic_vector(31 downto 0);
+
+	-- FAM aliases (docs/architecture.md#foreground-attribute-memory)
+	alias FAM_REG_FLIP_H is INT_FAM(31); -- Flip horizontally
+	alias FAM_REG_FLIP_V is INT_FAM(30); -- Flip vertically
+	alias FAM_REG_POS_H is INT_FAM(29 downto 21); -- horizontal position (offset by -16)
+	alias FAM_REG_POS_V is INT_FAM(20 downto 13); -- vertical position (offset by -16)
+	alias FAM_REG_COL_IDX is INT_FAM(12 downto 10); -- Palette index for tile
+	alias FAM_REG_TILE_IDX is INT_FAM(9 downto 0); -- Tilemap index
+
+	-- signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to FG canvas instead of viewport)
+	-- signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
+	-- signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
+	-- signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
+	-- signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
+	-- signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
+	-- signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
+	-- signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
+	-- signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
+	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
+begin
+	-- output drivers
+	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
+	TMM_ADDR <= R_TMM_ADDR;
+	T_TMM_DATA <= TMM_DATA;
+	-- CIDX combination
+	T_CIDX <= FAM_REG_COL_IDX & TMM_DATA_PAL_IDX;
+
+	-- FAM memory
+	FAM : component er_ram port map(
+		CLK => CLK,
+		RST => RESET,
+		WEN => FAM_WEN,
+		ADDR => FAM_ADDR,
+		DATA => FAM_DATA,
+		REG => INT_FAM);
+
+	-- -- -- FAM address calculations
+	-- -- PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(FG_SHIFT_X));
+	-- -- PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(FG_SHIFT_Y));
+	-- -- TILE_IDX_X <= PIXEL_ABS_X / 16;
+	-- -- TILE_IDX_Y <= PIXEL_ABS_Y / 16;
+	-- -- TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
+	-- -- TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
+	-- -- T_FAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_FG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_FAM_ADDR_WIDTH));
+
+	-- -- -- FAM data dependant calculations
+	-- -- TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
+	-- -- TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
+	-- -- transform: component ppu_sprite_transform port map(
+	-- -- 	XI => TRANSFORM_XI,
+	-- -- 	YI => TRANSFORM_YI,
+	-- -- 	FLIP_H => FAM_DATA_FLIP_H,
+	-- -- 	FLIP_V => FAM_DATA_FLIP_V,
+	-- -- 	XO => TRANSFORM_XO,
+	-- -- 	YO => TRANSFORM_YO);
+	-- -- TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
+	-- -- TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
+
+	-- -- TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
+	-- -- TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
+	-- -- PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
+
+	-- -- T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+
+	-- -- -- TMM DATA
+	-- -- with PIXEL_BIT_OFFSET select
+	-- -- 	TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
+	-- -- 	                    R_TMM_DATA(5 downto 3) when 1,
+	-- -- 	                    R_TMM_DATA(8 downto 6) when 2,
+	-- -- 	                    R_TMM_DATA(11 downto 9) when 3,
+	-- -- 	                    R_TMM_DATA(14 downto 12) when 4,
+	-- -- 	                    (others => '0') when others;
+
+	-- state machine (pipeline stage counter) + sync r/w
+	process(CLK, RESET)
+	begin
+		if RESET = '1' then
+			-- reset state
+			state <= PL_TMM_ADDR;
+			-- reset internal pipeline registers
+			R_TMM_ADDR <= (others => '0');
+			R_TMM_DATA <= (others => '0');
+		elsif rising_edge(CLK) then
+			case state is
+				when PL_TMM_ADDR =>
+					state <= PL_TMM_DATA;
+					R_TMM_ADDR <= T_TMM_ADDR;
+				when PL_TMM_DATA =>
+					state <= PL_TMM_ADDR;
+					R_TMM_DATA <= T_TMM_DATA;
+			end case;
+		end if;
+	end process;
+end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd b/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd
new file mode 100644
index 0000000..87c4f6e
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd
@@ -0,0 +1,15 @@
+library ieee;
+library work;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+use work.ppu_consts.all;
+
+entity ppu_sprite_fg_tb is
+end ppu_sprite_fg_tb;
+
+architecture Behavioral of ppu_sprite_fg_tb is
+begin
+end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index af6fbe7..7bc2f3c 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -160,9 +160,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_fg.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_bg"/>
+        <Option Name="TopModule" Val="ppu"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -223,9 +229,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_fg_tb.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_bg_tb"/>
+        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
diff --git a/docs/architecture.md b/docs/architecture.md
index 56bbb62..0c6fea7 100644
--- a/docs/architecture.md
+++ b/docs/architecture.md
@@ -134,6 +134,12 @@ Notable differences:
   
   Our game doesn't need this capability for any visual effects. Leaving this
   feature out will lead to a simpler hardware design
+- Sprites are positioned relative to the viewport, not the background layer
+  
+  This leads to a simpler hardware architecture for the foreground sprite
+  rendering component. Since the CPU is already likely to reposition all
+  foreground sprites on every frame, the position calculation is moved to
+  hardware to software.
 
 ## Hardware design schematics
 
-- 
cgit v1.2.3


From b9fa0b2333b4abe62cf19072eb0c38616997bb3c Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 23:28:31 +0100
Subject: WIP foreground sprite + `std_logic_vector` -> `unsigned` mess

---
 basys3/basys3.srcs/ppu_consts.vhd              | 20 +++---
 basys3/basys3.srcs/ppu_sprite_bg.vhd           | 50 ++++++--------
 basys3/basys3.srcs/ppu_sprite_fg.vhd           | 93 ++++++++++++--------------
 basys3/basys3.srcs/ppu_sprite_transform.vhd    | 16 ++---
 basys3/basys3.srcs/ppu_sprite_transform_tb.vhd | 32 ++++-----
 basys3/basys3.xpr                              | 15 ++---
 6 files changed, 106 insertions(+), 120 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 89b7a7a..722954d 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -2,7 +2,7 @@
 package ppu_consts is
 	constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
-	constant PPU_FG_SPRITE_COUNT : natural := 128; -- amount of foreground sprites
+	constant PPU_FG_SPRITE_COUNT : natural := 128; -- foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
 	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
 	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
@@ -17,18 +17,22 @@ package ppu_consts is
 	constant PPU_PAL_DATA_WIDTH : natural := 12; -- palette memory ram bus data width
 	constant PPU_AUX_ADDR_WIDTH : natural := 1; -- auxiliary memory ram bus address width
 	constant PPU_AUX_DATA_WIDTH : natural := 16; -- auxiliary memory ram bus data width
-	constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset
-	constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset
+	constant PPU_POS_H_WIDTH : natural := 9; -- bits for horizontal screen offset
+	constant PPU_POS_V_WIDTH : natural := 8; -- bits for vertical screen offset
 	constant PPU_SPRITE_WIDTH : natural := 16; -- sprite width (pixels)
 	constant PPU_SPRITE_HEIGHT : natural := 16; -- sprite height (pixels)
+	constant PPU_SPRITE_PIDX_WIDTH : natural := 8; -- bits needed to identify horizontal and vertical pixel within sprite
 	constant PPU_SPRITE_POS_H_WIDTH: natural := 4; -- bits needed to identify horizontal pixel within sprite
 	constant PPU_SPRITE_POS_V_WIDTH: natural := 4; -- bits needed to identify vertical pixel within sprite
 	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (pixels)
 	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (pixels)
-	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- amount of tiles (horizontally) on background canvas
-	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- amount of tiles (vertically) on background canvas
-	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- amount of bits needed to index a tile from TMM memory
-	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- amount of pixels defined in one word in TMM memory
-	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- amount of words needed for a single sprite
+	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- tiles (horizontally) on background canvas
+	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- tiles (vertically) on background canvas
+	constant PPU_BG_CANVAS_TILE_H_WIDTH : natural := 6; -- bits needed to describe horizontal bg tile index (grid coordinates)
+	constant PPU_BG_CANVAS_TILE_V_WIDTH : natural := 5; -- bits needed to describe vertical bg tile index (grid coordinates)
+	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- bits needed to index a tile from TMM memory
+	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- pixels defined in one word in TMM memory
+	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- words needed for a single sprite
+	constant PPU_PIXEL_BIT_WIDTH : natural := 3; -- bits needed to identify pixel in TMM word
 end package ppu_consts;
 
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index d8235f5..243fd93 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -31,11 +31,11 @@ end ppu_sprite_bg;
 
 architecture Behavioral of ppu_sprite_bg is
 	component ppu_sprite_transform port(
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
 	-- BAM and TMM in/out temp + registers
@@ -57,11 +57,9 @@ architecture Behavioral of ppu_sprite_bg is
 	-- auxiliary signals (temp variables)
 	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
 	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
-	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
-	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
-	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
+	signal TILE_PIDX_X, TRANS_TILE_PIDX_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0) := (others => '0'); -- x position of pixel within tile (local tile coords)
+	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- y position of pixel within tile (local tile coords)
+	signal TRANS_TILE_PIDX : integer := 0; -- index of pixel within tile (reading order)
 	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
 	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
@@ -77,32 +75,28 @@ begin
 	T_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
 
 	-- BAM address calculations
-	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
-	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
-	TILE_IDX_X <= PIXEL_ABS_X / 16;
-	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
-	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
-	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
+	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X)); -- pixel position relative to background canvas
+	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y)); -- pixel position relative to background canvas
+	TILE_IDX_X <= PIXEL_ABS_X / 16; -- tile grid index
+	TILE_IDX_Y <= PIXEL_ABS_Y / 16; -- tile grid index
+	TILE_PIDX_X <= to_unsigned(PIXEL_ABS_X - TILE_IDX_X * 16, TILE_PIDX_X'length); -- (sprite local) pixel coords
+	TILE_PIDX_Y <= to_unsigned(PIXEL_ABS_Y - TILE_IDX_Y * 16, TILE_PIDX_Y'length); -- (sprite local) pixel coords
 	T_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
 
 	-- BAM data dependant calculations
-	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
-	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
 	transform: component ppu_sprite_transform port map(
-		XI => TRANSFORM_XI,
-		YI => TRANSFORM_YI,
+		XI => TILE_PIDX_X,
+		YI => TILE_PIDX_Y,
 		FLIP_H => BAM_DATA_FLIP_H,
 		FLIP_V => BAM_DATA_FLIP_V,
-		XO => TRANSFORM_XO,
-		YO => TRANSFORM_YO);
-	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
-	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
+		XO => TRANS_TILE_PIDX_X,
+		YO => TRANS_TILE_PIDX_Y);
 
-	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
-
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+	-- TMM address calculations
+	TRANS_TILE_PIDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
index 340104a..c3cb59a 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -36,11 +36,11 @@ end ppu_sprite_fg;
 
 architecture Behavioral of ppu_sprite_fg is
 	component ppu_sprite_transform port(
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 	component er_ram -- exposed register RAM
 		generic(
@@ -77,15 +77,13 @@ architecture Behavioral of ppu_sprite_fg is
 	alias FAM_REG_COL_IDX is INT_FAM(12 downto 10); -- Palette index for tile
 	alias FAM_REG_TILE_IDX is INT_FAM(9 downto 0); -- Tilemap index
 
-	-- signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to FG canvas instead of viewport)
-	-- signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	-- signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
-	-- signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	-- signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
-	-- signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
-	-- signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
-	-- signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
-	-- signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
+	signal SPRITE_ACTIVE : std_logic := '0'; -- is pixel in bounding box of sprite
+	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to FG canvas instead of viewport)
+	signal TILE_PIDX_X, TRANS_TILE_PIDX_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
+	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
+	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
+	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
+	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
 begin
 	-- output drivers
@@ -104,42 +102,39 @@ begin
 		DATA => FAM_DATA,
 		REG => INT_FAM);
 
-	-- -- -- FAM address calculations
-	-- -- PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(FG_SHIFT_X));
-	-- -- PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(FG_SHIFT_Y));
-	-- -- TILE_IDX_X <= PIXEL_ABS_X / 16;
-	-- -- TILE_IDX_Y <= PIXEL_ABS_Y / 16;
-	-- -- TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
-	-- -- TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
-	-- -- T_FAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_FG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_FAM_ADDR_WIDTH));
-
-	-- -- -- FAM data dependant calculations
-	-- -- TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
-	-- -- TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
-	-- -- transform: component ppu_sprite_transform port map(
-	-- -- 	XI => TRANSFORM_XI,
-	-- -- 	YI => TRANSFORM_YI,
-	-- -- 	FLIP_H => FAM_DATA_FLIP_H,
-	-- -- 	FLIP_V => FAM_DATA_FLIP_V,
-	-- -- 	XO => TRANSFORM_XO,
-	-- -- 	YO => TRANSFORM_YO);
-	-- -- TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
-	-- -- TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
-
-	-- -- TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	-- -- TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	-- -- PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
-
-	-- -- T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
-
-	-- -- -- TMM DATA
-	-- -- with PIXEL_BIT_OFFSET select
-	-- -- 	TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
-	-- -- 	                    R_TMM_DATA(5 downto 3) when 1,
-	-- -- 	                    R_TMM_DATA(8 downto 6) when 2,
-	-- -- 	                    R_TMM_DATA(11 downto 9) when 3,
-	-- -- 	                    R_TMM_DATA(14 downto 12) when 4,
-	-- -- 	                    (others => '0') when others;
+	SPRITE_ACTIVE <= ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
+									 ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
+	                 ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
+									 ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH)));
+
+	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX); -- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
+
+	TILE_PIDX_X <= to_unsigned(unsigned(X) + 16 - to_unsigned(FAM_REG_POS_H, TILE_PIDX_X'length), TILE_PIDX_X'length); -- (sprite local) pixel coords
+	TILE_PIDX_Y <= to_unsigned(unsigned(Y) + 16 - to_unsigned(FAM_REG_POS_V, TILE_PIDX_Y'length), TILE_PIDX_Y'length); -- (sprite local) pixel coords
+
+	-- FAM data dependant calculations
+	transform: component ppu_sprite_transform port map(
+		XI => TILE_PIDX_X,
+		YI => TILE_PIDX_Y,
+		FLIP_H => FAM_REG_FLIP_H,
+		FLIP_V => FAM_REG_FLIP_V,
+		XO => TRANS_TILE_PIDX_X,
+		YO => TRANS_TILE_PIDX_Y);
+
+	-- TMM address calculations (sprite word start, word offset, and pixel offset)
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+
+	-- TMM DATA
+	with PIXEL_BIT_OFFSET select
+		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
+		                    R_TMM_DATA(5 downto 3) when 1,
+		                    R_TMM_DATA(8 downto 6) when 2,
+		                    R_TMM_DATA(11 downto 9) when 3,
+		                    R_TMM_DATA(14 downto 12) when 4,
+		                    (others => '0') when others;
 
 	-- state machine (pipeline stage counter) + sync r/w
 	process(CLK, RESET)
diff --git a/basys3/basys3.srcs/ppu_sprite_transform.vhd b/basys3/basys3.srcs/ppu_sprite_transform.vhd
index fa10b9b..f94616c 100644
--- a/basys3/basys3.srcs/ppu_sprite_transform.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_transform.vhd
@@ -5,19 +5,19 @@ use ieee.numeric_std.all;
 use work.ppu_consts.all;
 
 entity ppu_sprite_transform is port( -- flip sprites
-	XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-	YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+	XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+	YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 	FLIP_H, FLIP_V : in std_logic; -- flip sprite
-	XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-	YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+	XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+	YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 end ppu_sprite_transform;
 
 architecture Behavioral of ppu_sprite_transform is
-	signal FLIPPED_X : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal FLIPPED_Y : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal FLIPPED_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal FLIPPED_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 begin
-	FLIPPED_X <= std_logic_vector(to_unsigned(PPU_SPRITE_WIDTH-1 - to_integer(unsigned(XI)), PPU_SPRITE_POS_H_WIDTH));
-	FLIPPED_Y <= std_logic_vector(to_unsigned(PPU_SPRITE_HEIGHT-1 - to_integer(unsigned(YI)), PPU_SPRITE_POS_V_WIDTH));
+	FLIPPED_X <= to_unsigned(PPU_SPRITE_WIDTH-1, PPU_SPRITE_POS_H_WIDTH) - XI;
+	FLIPPED_Y <= to_unsigned(PPU_SPRITE_HEIGHT-1, PPU_SPRITE_POS_V_WIDTH) - YI;
 
 	XO <= FLIPPED_X when FLIP_V = '1' else XI;
 	YO <= FLIPPED_Y when FLIP_H = '1' else YI;
diff --git a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
index cec8c20..516a653 100644
--- a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
@@ -12,18 +12,18 @@ end ppu_sprite_transform_tb;
 
 architecture behavioral of ppu_sprite_transform_tb is
 	component ppu_sprite_transform port( -- flip sprites
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
-	signal XI : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal YI : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal XI : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal YI : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 	signal FLIP_H, FLIP_V : std_logic := '0';
-	signal XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal XO : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal YO : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 begin
 	uut : component ppu_sprite_transform
 		port map(
@@ -36,12 +36,12 @@ begin
 
 	tb : process
 	begin
-		XI <= std_logic_vector(to_unsigned(4, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(4, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(6, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		FLIP_H <= '1';
@@ -50,15 +50,15 @@ begin
 		FLIP_V <= '1';
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(8, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(6, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(8, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		FLIP_H <= '0';
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		wait; -- stop for simulator
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 7bc2f3c..d828223 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="42"/>
+    <Option Name="WTXSimLaunchSim" Val="55"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -168,7 +168,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu"/>
+        <Option Name="TopModule" Val="ppu_sprite_bg"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -247,18 +247,11 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -312,7 +305,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
-- 
cgit v1.2.3


From c09e9faf7e325184e435539d3e06d8340c67acd9 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Wed, 22 Feb 2023 16:13:12 +0100
Subject: WIP ppu fg sprite fetch logic

---
 basys3/basys3.srcs/ppu.vhd           |  25 ++++++--
 basys3/basys3.srcs/ppu_consts.vhd    |  23 ++++++-
 basys3/basys3.srcs/ppu_sprite_bg.vhd |   2 +-
 basys3/basys3.srcs/ppu_sprite_fg.vhd | 120 ++++++++++++++++++++++-------------
 basys3/basys3.xpr                    |  16 +++--
 5 files changed, 126 insertions(+), 60 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 22ee210..61c22aa 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -110,6 +110,7 @@ architecture Behavioral of ppu is
 			X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 			Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 			FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index)
+			VBLANK : in std_logic; -- fetch during vblank
 
 			-- internal memory block (FAM)
 			FAM_WEN : in std_logic; -- VRAM FAM write enable
@@ -188,6 +189,8 @@ architecture Behavioral of ppu is
 	signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
 	signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
 	signal FG_FETCH : std_logic;
+	signal TINY_VBLANK, TINY_VSYNC, TINY_HBLANK, TINY_HSYNC,
+	       NATIVE_VSYNC, NATIVE_HSYNC : std_logic;
 begin
 	SYSCLK <= CLK100;
 	SYSRST <= RESET;
@@ -201,6 +204,13 @@ begin
 	FAM_AI <= (others => '0');
 	PAL_AI <= (others => '0');
 
+	TVBLANK <= TINY_VBLANK;
+	TVSYNC <= TINY_VSYNC;
+	THBLANK <= TINY_HBLANK;
+	THSYNC <= TINY_HSYNC;
+	NVSYNC <= NATIVE_VSYNC;
+	NHSYNC <= NATIVE_HSYNC;
+
 	pipeline_clock_edge_generator : component ppu_pceg port map(
 		CLK => SYSCLK,
 		RESET => SYSRST,
@@ -273,12 +283,13 @@ begin
 		foreground_sprite : component ppu_sprite_fg
 			generic map( IDX => FG_IDX )
 			port map(
-				CLK => PL_SPRITE,
+				CLK => SYSCLK,
 				RESET => SYSRST,
 				OE => FG_EN(FG_IDX),
 				X => X,
 				Y => Y,
 				FETCH => FG_FETCH,
+				VBLANK => TINY_VBLANK,
 				FAM_WEN => FAM_WEN,
 				FAM_ADDR => FAM_AO,
 				FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
@@ -323,10 +334,10 @@ begin
 		RESET => SYSRST,
 		X => X,
 		Y => Y,
-		VSYNC => TVSYNC,
-		VBLANK => TVBLANK,
-		HSYNC => THSYNC,
-		HBLANK => THBLANK);
+		VSYNC => TINY_VSYNC,
+		VBLANK => TINY_VBLANK,
+		HSYNC => TINY_HSYNC,
+		HBLANK => TINY_HBLANK);
 
 	native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler)
 		CLK => SYSCLK,
@@ -340,6 +351,6 @@ begin
 		RO => R,
 		GO => G,
 		BO => B,
-		VSYNC => NVSYNC,
-		HSYNC => NHSYNC);
+		VSYNC => NATIVE_VSYNC,
+		HSYNC => NATIVE_HSYNC);
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 722954d..75b6168 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -1,12 +1,18 @@
+library ieee;
+use ieee.math_real.all;
+
 -- https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
 package ppu_consts is
+	-- utility functions
+	function ceil_log2(n : natural) return natural;
+
 	constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
 	constant PPU_FG_SPRITE_COUNT : natural := 128; -- foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
 	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
 	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
-	constant PPU_PALETTE_CIDX_WIDTH : natural := PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH; -- global palette index width
+	constant PPU_PALETTE_CIDX_WIDTH : natural := (PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH); -- global palette index width
 	constant PPU_TMM_ADDR_WIDTH : natural := 16; -- tilemap memory ram bus address width
 	constant PPU_TMM_DATA_WIDTH : natural := 15; -- tilemap memory ram bus data width
 	constant PPU_BAM_ADDR_WIDTH : natural := 11; -- background attribute memory ram bus address width
@@ -32,7 +38,18 @@ package ppu_consts is
 	constant PPU_BG_CANVAS_TILE_V_WIDTH : natural := 5; -- bits needed to describe vertical bg tile index (grid coordinates)
 	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- bits needed to index a tile from TMM memory
 	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- pixels defined in one word in TMM memory
-	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- words needed for a single sprite
+	constant PPU_SPRITE_WORD_COUNT : natural := 52; -- words needed for a single sprite
 	constant PPU_PIXEL_BIT_WIDTH : natural := 3; -- bits needed to identify pixel in TMM word
+	constant PPU_TILE_BIT_WIDTH : natural := (PPU_SPRITE_WIDTH * PPU_SPRITE_HEIGHT * PPU_PALETTE_COLOR_WIDTH); -- bits in single tile
+	constant PPU_TMM_CACHE_FETCH_C_COUNT : natural := PPU_SPRITE_WORD_COUNT + 1;
+	constant PPU_TMM_CACHE_FETCH_A_COUNT : natural := PPU_TMM_CACHE_FETCH_C_COUNT * PPU_FG_SPRITE_COUNT; -- amount of clocks to fetch new TMM cache
+	constant PPU_TMM_CACHE_FETCH_A_WIDTH : natural := ceil_log2(PPU_TMM_CACHE_FETCH_A_COUNT);
 end package ppu_consts;
-
+package body ppu_consts is
+	-- https://stackoverflow.com/questions/21783280/number-of-bits-to-represent-an-integer-in-vhdl
+	-- Returns number of bits required to represent val in binary vector
+	function ceil_log2(n : natural) return natural is
+	begin
+		return natural(integer(ceil(log2(real(n - 1)))));
+	end function;
+end package body ppu_consts;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 243fd93..dba5b8e 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -96,7 +96,7 @@ begin
 	TRANS_TILE_PIDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
 	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
 	PIXEL_BIT_OFFSET <= TRANS_TILE_PIDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_WORD_COUNT * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
index c3cb59a..7b39b1d 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -19,6 +19,7 @@ entity ppu_sprite_fg is -- foreground sprite
 		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 		FETCH : in std_logic; -- fetch sprite data from TMM
+		VBLANK : in std_logic; -- fetch during vblank
 
 		-- internal memory block (FAM)
 		FAM_WEN : in std_logic; -- VRAM FAM write enable
@@ -44,10 +45,10 @@ architecture Behavioral of ppu_sprite_fg is
 	end component;
 	component er_ram -- exposed register RAM
 		generic(
-			ADDR_W : natural := PPU_FAM_ADDR_WIDTH; -- ADDR line width
-			DATA_W : natural := PPU_FAM_DATA_WIDTH; -- DATA line width
-			ADDR_LOW : natural := IDX*2; -- starting address
-			ADDR_RANGE : natural := 2); -- amount of valid addresses after ADDR_LOW
+			ADDR_W : natural := 2; -- ADDR line width
+			DATA_W : natural := 2; -- DATA line width
+			ADDR_LOW : natural := 16#0000#; -- starting address
+			ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
 		port(
 			CLK : in std_logic; -- clock
 			RST : in std_logic; -- async memory clear
@@ -83,8 +84,13 @@ architecture Behavioral of ppu_sprite_fg is
 	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
 	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
 	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
-	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
+
+	-- TMM cache
+	signal TMM_CACHE_WEN : std_logic := '0';
+	signal TMM_CACHE_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_CACHE_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_CACHE : std_logic_vector((PPU_SPRITE_WORD_COUNT * PPU_TMM_DATA_WIDTH)-1 downto 0);
 begin
 	-- output drivers
 	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
@@ -94,25 +100,31 @@ begin
 	T_CIDX <= FAM_REG_COL_IDX & TMM_DATA_PAL_IDX;
 
 	-- FAM memory
-	FAM : component er_ram port map(
-		CLK => CLK,
-		RST => RESET,
-		WEN => FAM_WEN,
-		ADDR => FAM_ADDR,
-		DATA => FAM_DATA,
-		REG => INT_FAM);
-
-	SPRITE_ACTIVE <= ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
-									 ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
-	                 ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
-									 ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH)));
-
-	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX); -- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
-
-	TILE_PIDX_X <= to_unsigned(unsigned(X) + 16 - to_unsigned(FAM_REG_POS_H, TILE_PIDX_X'length), TILE_PIDX_X'length); -- (sprite local) pixel coords
-	TILE_PIDX_Y <= to_unsigned(unsigned(Y) + 16 - to_unsigned(FAM_REG_POS_V, TILE_PIDX_Y'length), TILE_PIDX_Y'length); -- (sprite local) pixel coords
-
-	-- FAM data dependant calculations
+	FAM : component er_ram
+		generic map(
+			ADDR_W => PPU_FAM_ADDR_WIDTH,
+			DATA_W => PPU_FAM_DATA_WIDTH,
+			ADDR_LOW => IDX*2,
+			ADDR_RANGE => 2)
+		port map(
+			CLK => CLK,
+			RST => RESET,
+			WEN => FAM_WEN,
+			ADDR => FAM_ADDR,
+			DATA => FAM_DATA,
+			REG => INT_FAM);
+
+	-- pixel position within bounding box of sprite
+	SPRITE_ACTIVE <= '1' when ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
+	                          ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
+	                          ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
+	                          ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH))) else '0';
+
+	-- (sprite local) pixel coords
+	TILE_PIDX_X <= resize(unsigned(X) + 16 - resize(unsigned(FAM_REG_POS_H), TILE_PIDX_X'length), TILE_PIDX_X'length);
+	TILE_PIDX_Y <= resize(unsigned(Y) + 16 - resize(unsigned(FAM_REG_POS_V), TILE_PIDX_Y'length), TILE_PIDX_Y'length);
+
+	-- transform local coords
 	transform: component ppu_sprite_transform port map(
 		XI => TILE_PIDX_X,
 		YI => TILE_PIDX_Y,
@@ -121,23 +133,39 @@ begin
 		XO => TRANS_TILE_PIDX_X,
 		YO => TRANS_TILE_PIDX_Y);
 
-	-- TMM address calculations (sprite word start, word offset, and pixel offset)
-	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	-- pixel index
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X);
+	-- palette color at pixel
+	TMM_DATA_PAL_IDX <= TMM_CACHE(TRANS_TILE_PIXEL_IDX * integer(PPU_PALETTE_COLOR_WIDTH) + integer(PPU_PALETTE_COLOR_WIDTH)-1 downto TRANS_TILE_PIXEL_IDX * integer(PPU_PALETTE_COLOR_WIDTH));
+	-- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
+	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX);
+
+	-- FETCH LOGIC BELOW
+
+	-- TTM cache
+	ttm_cache : component er_ram
+		generic map(
+			ADDR_W => PPU_TMM_ADDR_WIDTH,
+			DATA_W => PPU_TMM_DATA_WIDTH,
+			ADDR_LOW => 0,
+			ADDR_RANGE => PPU_SPRITE_WORD_COUNT)
+		port map(
+			CLK => CLK,
+			RST => RESET,
+			WEN => TMM_CACHE_WEN,
+			ADDR => TMM_CACHE_ADDR,
+			DATA => TMM_CACHE_DATA,
+			REG => TMM_CACHE);
+
 	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
-	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
-
-	-- TMM DATA
-	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
-		                    R_TMM_DATA(5 downto 3) when 1,
-		                    R_TMM_DATA(8 downto 6) when 2,
-		                    R_TMM_DATA(11 downto 9) when 3,
-		                    R_TMM_DATA(14 downto 12) when 4,
-		                    (others => '0') when others;
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_WORD_COUNT * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+
 
 	-- state machine (pipeline stage counter) + sync r/w
 	process(CLK, RESET)
+		constant TMM_FETCH_CLK_RANGE_BEGIN : natural := PPU_TMM_CACHE_FETCH_C_COUNT * IDX;
+		variable TMM_FETCH_CTR : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
+		variable TMM_FETCH_CTR_REL : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
 	begin
 		if RESET = '1' then
 			-- reset state
@@ -146,14 +174,16 @@ begin
 			R_TMM_ADDR <= (others => '0');
 			R_TMM_DATA <= (others => '0');
 		elsif rising_edge(CLK) then
-			case state is
-				when PL_TMM_ADDR =>
-					state <= PL_TMM_DATA;
-					R_TMM_ADDR <= T_TMM_ADDR;
-				when PL_TMM_DATA =>
-					state <= PL_TMM_ADDR;
-					R_TMM_DATA <= T_TMM_DATA;
-			end case;
+			TMM_FETCH_CTR := (others => '0') when FETCH = '0' else TMM_FETCH_CTR + 1;
+			TMM_FETCH_CTR_REL := TMM_FETCH_CTR - TMM_FETCH_CLK_RANGE_BEGIN;
+
+			if FETCH = '1' and TMM_FETCH_CTR >= TMM_FETCH_CLK_RANGE_BEGIN and TMM_FETCH_CTR < (TMM_FETCH_CLK_RANGE_BEGIN + PPU_TMM_CACHE_FETCH_C_COUNT) then
+				TMM_CACHE_WEN <= '1';
+				R_TMM_DATA <= T_TMM_DATA;
+				T_TMM_ADDR <= R_TMM_ADDR;
+			else
+				TMM_CACHE_WEN <= '0';
+			end if;
 		end if;
 	end process;
 end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index d828223..813b3e2 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="55"/>
+    <Option Name="WTXSimLaunchSim" Val="57"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -168,7 +168,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_bg"/>
+        <Option Name="TopModule" Val="ppu"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -237,7 +237,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
+        <Option Name="TopModule" Val="er_ram_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -252,6 +252,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -305,7 +313,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
-- 
cgit v1.2.3


From e7fbeb1a6071db070c4c2b21c4c5ed70d53e269b Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Thu, 23 Feb 2023 13:21:31 +0100
Subject: ppu foreground sprite working and ~50% tested

---
 basys3/basys3.srcs/ppu.vhd              |   4 +-
 basys3/basys3.srcs/ppu_sprite_fg.vhd    |  67 +++++++++--------
 basys3/basys3.srcs/ppu_sprite_fg_tb.vhd | 125 ++++++++++++++++++++++++++++++++
 basys3/basys3.xpr                       |   4 +-
 4 files changed, 164 insertions(+), 36 deletions(-)

(limited to 'basys3/basys3.xpr')

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 61c22aa..9cf1bc0 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -104,12 +104,12 @@ architecture Behavioral of ppu is
 			IDX : natural := 0);
 		port(
 			-- inputs
-			CLK : in std_logic; -- pipeline clock
+			CLK : in std_logic; -- system clock
 			RESET : in std_logic; -- reset internal memory and clock counters
 			OE : in std_logic; -- output enable (of CIDX)
 			X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 			Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-			FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index)
+			FETCH : in std_logic; -- fetch sprite data from TMM
 			VBLANK : in std_logic; -- fetch during vblank
 
 			-- internal memory block (FAM)
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
index 7b39b1d..af7cfa3 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -13,7 +13,6 @@ entity ppu_sprite_fg is -- foreground sprite
 	port(
 		-- inputs
 		CLK : in std_logic; -- system clock
-		PL_CLK : in std_logic; -- pipeline clock
 		RESET : in std_logic; -- reset internal memory and clock counters
 		OE : in std_logic; -- output enable (of CIDX)
 		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
@@ -58,13 +57,9 @@ architecture Behavioral of ppu_sprite_fg is
 			REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output
 	end component;
 
-	-- FAM and TMM in/out temp + registers
-	signal T_TMM_ADDR, R_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal T_TMM_DATA, R_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	-- state machine for synchronizing pipeline stages
-	type states is (PL_TMM_ADDR, PL_TMM_DATA);
-	signal state : states := PL_TMM_ADDR;
+	-- FAM and TMM in/out lines
+	signal T_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
 
 	-- auxiliary signals (temp variables)
 	signal T_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- output color buffer/register
@@ -86,16 +81,14 @@ architecture Behavioral of ppu_sprite_fg is
 	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
 
-	-- TMM cache
-	signal TMM_CACHE_WEN : std_logic := '0';
+	-- TMM cache lines
+	signal TMM_CACHE_WEN, TMM_CACHE_UPDATE_TURN : std_logic := '0';
 	signal TMM_CACHE_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal TMM_CACHE_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
 	signal TMM_CACHE : std_logic_vector((PPU_SPRITE_WORD_COUNT * PPU_TMM_DATA_WIDTH)-1 downto 0);
 begin
 	-- output drivers
 	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
-	TMM_ADDR <= R_TMM_ADDR;
-	T_TMM_DATA <= TMM_DATA;
 	-- CIDX combination
 	T_CIDX <= FAM_REG_COL_IDX & TMM_DATA_PAL_IDX;
 
@@ -141,6 +134,8 @@ begin
 	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX);
 
 	-- FETCH LOGIC BELOW
+	TMM_ADDR <= T_TMM_ADDR when TMM_CACHE_UPDATE_TURN else (others => 'Z');
+	T_TMM_DATA <= TMM_DATA;
 
 	-- TTM cache
 	ttm_cache : component er_ram
@@ -157,32 +152,40 @@ begin
 			DATA => TMM_CACHE_DATA,
 			REG => TMM_CACHE);
 
-	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_WORD_COUNT * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
-
-
-	-- state machine (pipeline stage counter) + sync r/w
-	process(CLK, RESET)
-		constant TMM_FETCH_CLK_RANGE_BEGIN : natural := PPU_TMM_CACHE_FETCH_C_COUNT * IDX;
-		variable TMM_FETCH_CTR : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
-		variable TMM_FETCH_CTR_REL : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
+	-- fetch machine, should do the following (offset data read by one clock -> propagation/lookup delay):
+	-- CLK[53 * IDX + 0] (addr = 0)
+	-- CLK[53 * IDX + 1] (addr = 1, read data[0])
+	-- CLK[53 * IDX + 2] (addr = 2, read data[1]), etc
+	-- a full tile is 52 words, but since the offset is 1 clock, a total copy takes 53 clock cycles
+	process(CLK, RESET, FETCH)
+		constant TMM_FETCH_CLK_RANGE_BEGIN : natural := PPU_TMM_CACHE_FETCH_C_COUNT * IDX; -- fetch CLK count for copying this module's sprite from TMM
+		variable TMM_FETCH_CTR : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0'); -- CLK counter while FETCH=1
+		variable TMM_FETCH_CTR_REL : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0'); -- CLK counter relative for sprite[IDX]
 	begin
-		if RESET = '1' then
-			-- reset state
-			state <= PL_TMM_ADDR;
-			-- reset internal pipeline registers
-			R_TMM_ADDR <= (others => '0');
-			R_TMM_DATA <= (others => '0');
+		if RESET = '1' or FETCH = '0' then
+			TMM_FETCH_CTR := (others => '0');
+			TMM_FETCH_CTR_REL := (others => '0');
+			TMM_CACHE_WEN <= '0';
+			TMM_CACHE_UPDATE_TURN <= '0';
 		elsif rising_edge(CLK) then
-			TMM_FETCH_CTR := (others => '0') when FETCH = '0' else TMM_FETCH_CTR + 1;
+			TMM_FETCH_CTR := TMM_FETCH_CTR + 1;
 			TMM_FETCH_CTR_REL := TMM_FETCH_CTR - TMM_FETCH_CLK_RANGE_BEGIN;
 
-			if FETCH = '1' and TMM_FETCH_CTR >= TMM_FETCH_CLK_RANGE_BEGIN and TMM_FETCH_CTR < (TMM_FETCH_CLK_RANGE_BEGIN + PPU_TMM_CACHE_FETCH_C_COUNT) then
-				TMM_CACHE_WEN <= '1';
-				R_TMM_DATA <= T_TMM_DATA;
-				T_TMM_ADDR <= R_TMM_ADDR;
+			if TMM_FETCH_CTR >= TMM_FETCH_CLK_RANGE_BEGIN and
+			   TMM_FETCH_CTR < (TMM_FETCH_CLK_RANGE_BEGIN + PPU_TMM_CACHE_FETCH_C_COUNT) then
+				TMM_CACHE_UPDATE_TURN <= '1';
+				if TMM_FETCH_CTR_REL < PPU_TMM_CACHE_FETCH_C_COUNT - 1 then -- calculate address until second to last clock
+					T_TMM_ADDR <= std_logic_vector(resize(TMM_FETCH_CTR - IDX, T_TMM_ADDR'length));
+					TMM_CACHE_ADDR <= std_logic_vector(resize(TMM_FETCH_CTR_REL - 1, TMM_CACHE_ADDR'length));
+				end if;
+
+				if TMM_FETCH_CTR_REL > 0 then -- read offset
+					TMM_CACHE_DATA <= T_TMM_DATA;
+					TMM_CACHE_WEN <= '1';
+				end if;
 			else
 				TMM_CACHE_WEN <= '0';
+				TMM_CACHE_UPDATE_TURN <= '0';
 			end if;
 		end if;
 	end process;
diff --git a/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd b/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd
index 87c4f6e..19b9f35 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg_tb.vhd
@@ -11,5 +11,130 @@ entity ppu_sprite_fg_tb is
 end ppu_sprite_fg_tb;
 
 architecture Behavioral of ppu_sprite_fg_tb is
+	component ppu_sprite_fg -- foreground sprite
+		generic (
+			IDX : natural := 0); -- sprite index number
+		port(
+			-- inputs
+			CLK : in std_logic; -- system clock
+			RESET : in std_logic; -- reset internal memory and clock counters
+			OE : in std_logic; -- output enable (of CIDX)
+			X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+			Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+			FETCH : in std_logic; -- fetch sprite data from TMM
+			VBLANK : in std_logic; -- fetch during vblank
+
+			-- internal memory block (FAM)
+			FAM_WEN : in std_logic; -- VRAM FAM write enable
+			FAM_ADDR : in std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0); -- VRAM fam address
+			FAM_DATA : in std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0); -- VRAM fam data
+
+			-- used memory blocks
+			TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+			TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+			-- outputs
+			CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- output color
+			HIT : out std_logic); -- current pixel is not transparent
+	end component;
+	signal CLK : std_logic := '0';
+	signal RESET : std_logic := '0';
+	signal OE : std_logic := '0';
+	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
+	signal FETCH : std_logic := '0';
+	signal VBLANK : std_logic := '0';
+	signal FAM_WEN : std_logic := '0';
+	signal FAM_ADDR : std_logic_vector(PPU_FAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal FAM_DATA : std_logic_vector(PPU_FAM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	signal TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');
+	signal HIT : std_logic;
+
+	signal CLK_I : unsigned(31 downto 0) := (others => '0');
 begin
+	uut: component ppu_sprite_fg
+		generic map( IDX => 2 )
+		port map(
+			CLK => CLK,
+			RESET => RESET,
+			OE => OE,
+			X => X,
+			Y => Y,
+			FETCH => FETCH,
+			VBLANK => VBLANK,
+			FAM_WEN => FAM_WEN,
+			FAM_ADDR => FAM_ADDR,
+			FAM_DATA => FAM_DATA,
+			TMM_ADDR => TMM_ADDR,
+			TMM_DATA => TMM_DATA,
+			CIDX => CIDX,
+			HIT => HIT);
+
+	tb : process
+	begin
+		-- initialize TMM cache
+		RESET <= '1'; wait for 1 ns; RESET <= '0'; wait for 1 ns;
+
+		OE <= '1';
+		VBLANK <= '0';
+		FETCH <= '0';
+
+		-- FAM contents:
+		-- flip horizontally
+		-- xy -> (42-16, 8-16) = (26, -8)
+		-- palette index 2
+		-- tilemap index 460 (0x1cc)
+		-- = hex((1 << 31) | (0 << 30) | (42 << 21) | (8 << 13) | (2 << 10) | (460 << 0))
+		FAM_WEN <= '1';
+		FAM_ADDR <= std_logic_vector(to_unsigned(16#0005#, FAM_ADDR'length));
+		FAM_DATA <= std_logic_vector(to_unsigned(16#8541#, FAM_DATA'length));
+		CLK <= '1'; wait for 1 ns; CLK <= '0'; wait for 1 ns;
+		FAM_ADDR <= std_logic_vector(to_unsigned(16#0004#, FAM_ADDR'length));
+		FAM_DATA <= std_logic_vector(to_unsigned(16#09cc#, FAM_DATA'length));
+		CLK <= '1'; wait for 1 ns; CLK <= '0'; wait for 1 ns;
+		FAM_WEN <= '0';
+
+		for i in 0 to 32 loop
+			if i = 0 then
+				X <= std_logic_vector(to_unsigned(25, X'length));
+				Y <= std_logic_vector(to_unsigned(60, Y'length));
+			end if;
+
+			if i = 3 then
+				X <= std_logic_vector(to_unsigned(29, X'length));
+				Y <= std_logic_vector(to_unsigned(4, Y'length));
+			end if;
+	
+			wait for 5 ns; CLK <= '1'; wait for 5 ns; CLK <= '0';
+		end loop;
+
+		wait for 1 ns;
+		RESET <= '1';
+		wait for 10 ns;
+		RESET <= '0';
+		VBLANK <= '1';
+		FETCH <= '1';
+		wait for 1 ns;
+
+		-- FETCH check
+		for i in 0 to 500 loop
+			CLK_I <= to_unsigned(i, 32);
+			-- if i > 10 then
+			-- 	OE <= '1';
+			-- end if;
+			-- if i > 20 then
+			-- 	RESET <= '1';
+			-- end if;
+
+			TMM_DATA <= std_logic_vector(to_unsigned(i - 106, TMM_DATA'length));
+	
+			CLK <= '1';
+			wait for 1 ns;
+			CLK <= '0';
+			wait for 1 ns;
+		end loop;
+		wait; -- stop for simulator
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 813b3e2..0c452cf 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="57"/>
+    <Option Name="WTXSimLaunchSim" Val="113"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -237,7 +237,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="er_ram_tb"/>
+        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
-- 
cgit v1.2.3