From 27b39499095ccb7e7e73a78776946b60fc96fb05 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 20 Feb 2023 17:13:06 +0100
Subject: PPU background sprite component done (but unverified)

---
 basys3/basys3.srcs/ppu_sprite_bg.vhd | 150 +++++++++++++++++++++++++++++++++++
 1 file changed, 150 insertions(+)
 create mode 100644 basys3/basys3.srcs/ppu_sprite_bg.vhd

(limited to 'basys3/basys3.srcs/ppu_sprite_bg.vhd')

diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
new file mode 100644
index 0000000..a92c401
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -0,0 +1,150 @@
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.ppu_consts.all;
+
+entity ppu_sprite_bg is port(
+	-- inputs
+	CLK : in std_logic; -- pipeline clock
+	RESET : in std_logic; -- reset clock counter
+	OE : in std_logic; -- output enable (of CIDX)
+	X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+	Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+	
+	-- aux inputs
+	BG_SHIFT_X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
+	BG_SHIFT_Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
+
+	-- used memory blocks
+	BAM_ADDR : out std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0);
+	BAM_DATA : in std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+	TMM_ADDR : out std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0);
+	TMM_DATA : in std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+	-- outputs
+	CIDX : out std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0)); -- output color
+end ppu_sprite_bg;
+
+architecture Behavioral of ppu_sprite_bg is
+	component ppu_sprite_transform port(
+		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		FLIP_H, FLIP_V : in std_logic; -- flip sprite
+		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+	end component;
+
+	signal O_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal I_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
+	signal O_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal I_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
+
+	signal FLIP_H, FLIP_V : std_logic := '0';
+	signal TMM_IDX : std_logic_vector(PPU_TILE_INDEX_WIDTH-1 downto 0) := (others => '0');
+
+	alias BAM_DATA_COL_IDX is I_BAM_DATA(12 downto 10);
+	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0);
+	signal O_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');
+
+	type states is (PL_BAM_ADDR, PL_BAM_DATA, PL_TMM_ADDR, PL_TMM_DATA);
+	signal state, next_state : states := PL_BAM_ADDR;
+
+	-- docs/architecture.md#background-attribute-memory
+	alias BAM_DATA_FLIP_H is I_BAM_DATA(14);
+	alias BAM_DATA_FLIP_V is I_BAM_DATA(13);
+	alias BAM_DATA_TILE_IDX is I_BAM_DATA(9 downto 0);
+
+	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
+	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
+	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile
+	signal TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile
+	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
+	signal TILEMAP_WORD_OFFSET : integer := 0;
+	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal PIXEL_BIT_OFFSET : integer := 0;
+begin
+	-- CIDX tri-state driver
+	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
+
+	-- internal line separators
+	FLIP_H <= BAM_DATA_FLIP_H;
+	FLIP_V <= BAM_DATA_FLIP_V;
+	O_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
+
+	-- BAM ADDR
+	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
+	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
+	TILE_IDX_X <= PIXEL_ABS_X / 16;
+	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
+	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
+	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
+	O_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
+
+	-- BAM DATA + FAM ADDR
+	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
+	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
+	transform: component ppu_sprite_transform port map(
+		XI => TRANSFORM_XI,
+		YI => TRANSFORM_YI,
+		FLIP_H => FLIP_H,
+		FLIP_V => FLIP_V,
+		XO => TRANSFORM_XO,
+		YO => TRANSFORM_YO);
+	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
+	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
+
+	TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
+	TILEMAP_WORD_OFFSET <= TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
+	PIXEL_BIT_OFFSET <= TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
+
+	O_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+
+	-- TMM DATA
+	with PIXEL_BIT_OFFSET select
+		TMM_DATA_PAL_IDX <= TMM_DATA(2 downto 0) when 0,
+		                    TMM_DATA(5 downto 3) when 1,
+		                    TMM_DATA(8 downto 6) when 2,
+		                    TMM_DATA(11 downto 9) when 3,
+		                    TMM_DATA(14 downto 12) when 4,
+		                    (others => '0') when others;
+
+	-- state machine (pipeline stage counter)
+	fsm: process(CLK, RESET)
+	begin
+		if RESET = '1' then
+			state <= PL_BAM_ADDR;
+		elsif rising_edge(CLK) then
+			state <= next_state;
+		end if;
+	end process;
+
+	-- sync read/write
+	process(state)
+	begin
+		next_state <= state;
+		case state is
+			when PL_BAM_ADDR =>
+				next_state <= PL_BAM_DATA;
+				BAM_ADDR <= O_BAM_ADDR;
+
+			when PL_BAM_DATA =>
+				next_state <= PL_TMM_ADDR;
+				I_BAM_DATA <= BAM_DATA;
+				
+			when PL_TMM_ADDR =>
+				next_state <= PL_TMM_DATA;
+				TMM_ADDR <= O_TMM_ADDR;
+
+			when PL_TMM_DATA =>
+				next_state <= PL_BAM_ADDR;
+				I_TMM_DATA <= TMM_DATA;
+
+				
+		end case;
+	end process;
+
+end Behavioral;
-- 
cgit v1.2.3


From 55c3e36b2367daf6b9b3f894fb6a65b6d6b18158 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 14:21:33 +0100
Subject: PPU debugged and working (but with unwanted latches)

---
 basys3/basys3.srcs/ppu_sprite_bg.vhd    | 20 +++++++++++++++-----
 basys3/basys3.srcs/ppu_sprite_bg_tb.vhd | 25 +++++++++++++++++++++++--
 basys3/basys3.xpr                       |  8 +++++++-
 3 files changed, 45 insertions(+), 8 deletions(-)

(limited to 'basys3/basys3.srcs/ppu_sprite_bg.vhd')

diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index a92c401..391083f 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -67,6 +67,8 @@ architecture Behavioral of ppu_sprite_bg is
 	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 	signal PIXEL_BIT_OFFSET : integer := 0;
 begin
+	-- TODO: fix latches
+
 	-- CIDX tri-state driver
 	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
 
@@ -105,18 +107,26 @@ begin
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= TMM_DATA(2 downto 0) when 0,
-		                    TMM_DATA(5 downto 3) when 1,
-		                    TMM_DATA(8 downto 6) when 2,
-		                    TMM_DATA(11 downto 9) when 3,
-		                    TMM_DATA(14 downto 12) when 4,
+		TMM_DATA_PAL_IDX <= I_TMM_DATA(2 downto 0) when 0,
+		                    I_TMM_DATA(5 downto 3) when 1,
+		                    I_TMM_DATA(8 downto 6) when 2,
+		                    I_TMM_DATA(11 downto 9) when 3,
+		                    I_TMM_DATA(14 downto 12) when 4,
 		                    (others => '0') when others;
 
 	-- state machine (pipeline stage counter)
 	fsm: process(CLK, RESET)
 	begin
 		if RESET = '1' then
+			-- reset state
 			state <= PL_BAM_ADDR;
+			-- reset internal pipeline registers
+			-- O_BAM_ADDR <= (others => '0');
+			-- I_BAM_DATA <= (others => '0');
+			-- O_TMM_ADDR <= (others => '0');
+			-- I_TMM_DATA <= (others => '0');
+			-- reset working color register
+			-- O_CIDX <= (others => '0');
 		elsif rising_edge(CLK) then
 			state <= next_state;
 		end if;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
index 2dee2fe..65da15c 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg_tb.vhd
@@ -59,13 +59,34 @@ begin
 		TMM_DATA => TMM_DATA,
 		CIDX => CIDX);
 
-	BAM_DATA <= std_logic_vector(to_unsigned(16#4814#, PPU_BAM_DATA_WIDTH));  -- hex((1 << 14) | (0 << 13) | (2 << 10) | (20 << 0))
-	TMM_DATA <= std_logic_vector(to_unsigned(16#ffff#, PPU_TMM_DATA_WIDTH));
+	-- inputs
+	-- BAM_DATA -> FLIP_H + palette index 2 + tilemap index 10
+	-- TMM_DATA -> all pixels color 7
+	-- X -> 25
+	-- Y -> 60
+	-- BG_SHIFT_X -> 3
+	-- BG_SHIFT_Y -> 3
+	BAM_DATA <= 15x"4814"; -- hex((1 << 14) | (0 << 13) | (2 << 10) | (20 << 0))
+	TMM_DATA <= 15x"7e3f"; -- hex(0x7fff & ~(0b111 << 6))
 	X <= std_logic_vector(to_unsigned(25, PPU_POS_H_WIDTH));
 	Y <= std_logic_vector(to_unsigned(60, PPU_POS_V_WIDTH));
 	BG_SHIFT_X <= std_logic_vector(to_unsigned(3, PPU_POS_H_WIDTH));
 	BG_SHIFT_Y <= std_logic_vector(to_unsigned(3, PPU_POS_V_WIDTH));
 
+	-- expected outputs:
+	-- absolute pixel coordinates -> (28, 63)
+	-- absolute background canvas tile index coordinates -> (1, 3)
+	-- tile index -> 3 * 40 + 1 = 121
+	-- BAM_ADDR => 121 (OK)
+	-- sprite local coordinates -> (12, 15)
+	-- transformed local coordinates -> (12, 0) (apply FLIP_H)
+	-- pixel index -> 0 * 16 + 12 = 12
+	-- pixel word address -> 52 * 20 + 12//5 -> 1042
+	-- TMM_ADDR => 1042 (OK)
+	-- pixel bits -> [pixel n+] = 12 % 5 = 2 -> 8 downto 6
+	-- cidx should be -- (2 << 3) | (0 << 0) = 16
+	-- CIDX => 16 (OK)
+
 	tb : process
 	begin
 		for i in 0 to 32 loop
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 556c73e..c79fd58 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="31"/>
+    <Option Name="WTXSimLaunchSim" Val="39"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -217,6 +217,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/ppu_sprite_transform_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="ppu_sprite_bg_tb"/>
-- 
cgit v1.2.3


From 9ab2a3d4b4304a4f489e100a6b66d6ee414143e7 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 15:32:11 +0100
Subject: background sprite component done, tested, and working without latches

---
 basys3/basys3.srcs/ppu_sprite_bg.vhd | 144 ++++++++++++++++-------------------
 basys3/basys3.xpr                    |  13 +++-
 2 files changed, 75 insertions(+), 82 deletions(-)

(limited to 'basys3/basys3.srcs/ppu_sprite_bg.vhd')

diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 391083f..d8235f5 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -6,6 +6,7 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use work.ppu_consts.all;
 
+-- TODO: add input stable / output stable pipeline stages if this doesn't work with propagation delays
 entity ppu_sprite_bg is port(
 	-- inputs
 	CLK : in std_logic; -- pipeline clock
@@ -37,124 +38,107 @@ architecture Behavioral of ppu_sprite_bg is
 		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
-	signal O_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal I_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0);
-	signal O_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal I_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0);
-
-	signal FLIP_H, FLIP_V : std_logic := '0';
-	signal TMM_IDX : std_logic_vector(PPU_TILE_INDEX_WIDTH-1 downto 0) := (others => '0');
-
-	alias BAM_DATA_COL_IDX is I_BAM_DATA(12 downto 10);
-	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0);
-	signal O_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');
+	-- BAM and TMM in/out temp + registers
+	signal T_BAM_ADDR, R_BAM_ADDR : std_logic_vector(PPU_BAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_BAM_DATA, R_BAM_DATA : std_logic_vector(PPU_BAM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_ADDR, R_TMM_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal T_TMM_DATA, R_TMM_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
 
+	-- state machine for synchronizing pipeline stages
 	type states is (PL_BAM_ADDR, PL_BAM_DATA, PL_TMM_ADDR, PL_TMM_DATA);
-	signal state, next_state : states := PL_BAM_ADDR;
+	signal state : states := PL_BAM_ADDR;
 
 	-- docs/architecture.md#background-attribute-memory
-	alias BAM_DATA_FLIP_H is I_BAM_DATA(14);
-	alias BAM_DATA_FLIP_V is I_BAM_DATA(13);
-	alias BAM_DATA_TILE_IDX is I_BAM_DATA(9 downto 0);
+	alias BAM_DATA_FLIP_H is R_BAM_DATA(14); -- flip horizontally
+	alias BAM_DATA_FLIP_V is R_BAM_DATA(13); -- flip vertically
+	alias BAM_DATA_TILE_IDX is R_BAM_DATA(9 downto 0); -- tilemap tile index
+	alias BAM_DATA_COL_IDX is R_BAM_DATA(12 downto 10); -- palette for sprite
 
+	-- auxiliary signals (temp variables)
 	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
 	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile
-	signal TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile
+	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
 	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	signal TILEMAP_WORD_OFFSET : integer := 0;
-	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
-	signal PIXEL_BIT_OFFSET : integer := 0;
+	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
+	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
+	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
+	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
+	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
+	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
+	signal T_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- output color buffer/register
 begin
-	-- TODO: fix latches
-
-	-- CIDX tri-state driver
-	CIDX <= O_CIDX when OE = '1' else (others => 'Z');
-
-	-- internal line separators
-	FLIP_H <= BAM_DATA_FLIP_H;
-	FLIP_V <= BAM_DATA_FLIP_V;
-	O_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
-
-	-- BAM ADDR
+	-- output drivers
+	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
+	BAM_ADDR <= R_BAM_ADDR;
+	TMM_ADDR <= R_TMM_ADDR;
+	T_BAM_DATA <= BAM_DATA;
+	T_TMM_DATA <= TMM_DATA;
+	-- CIDX combination
+	T_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
+
+	-- BAM address calculations
 	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
 	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
 	TILE_IDX_X <= PIXEL_ABS_X / 16;
 	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
 	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
 	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
-	O_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
+	T_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
 
-	-- BAM DATA + FAM ADDR
+	-- BAM data dependant calculations
 	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
 	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
 	transform: component ppu_sprite_transform port map(
 		XI => TRANSFORM_XI,
 		YI => TRANSFORM_YI,
-		FLIP_H => FLIP_H,
-		FLIP_V => FLIP_V,
+		FLIP_H => BAM_DATA_FLIP_H,
+		FLIP_V => BAM_DATA_FLIP_V,
 		XO => TRANSFORM_XO,
 		YO => TRANSFORM_YO);
 	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
 	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
 
-	TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	TILEMAP_WORD_OFFSET <= TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	PIXEL_BIT_OFFSET <= TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
 
-	O_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= I_TMM_DATA(2 downto 0) when 0,
-		                    I_TMM_DATA(5 downto 3) when 1,
-		                    I_TMM_DATA(8 downto 6) when 2,
-		                    I_TMM_DATA(11 downto 9) when 3,
-		                    I_TMM_DATA(14 downto 12) when 4,
+		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
+		                    R_TMM_DATA(5 downto 3) when 1,
+		                    R_TMM_DATA(8 downto 6) when 2,
+		                    R_TMM_DATA(11 downto 9) when 3,
+		                    R_TMM_DATA(14 downto 12) when 4,
 		                    (others => '0') when others;
 
-	-- state machine (pipeline stage counter)
-	fsm: process(CLK, RESET)
+	-- state machine (pipeline stage counter) + sync r/w
+	process(CLK, RESET)
 	begin
 		if RESET = '1' then
 			-- reset state
 			state <= PL_BAM_ADDR;
 			-- reset internal pipeline registers
-			-- O_BAM_ADDR <= (others => '0');
-			-- I_BAM_DATA <= (others => '0');
-			-- O_TMM_ADDR <= (others => '0');
-			-- I_TMM_DATA <= (others => '0');
-			-- reset working color register
-			-- O_CIDX <= (others => '0');
+			R_BAM_ADDR <= (others => '0');
+			R_BAM_DATA <= (others => '0');
+			R_TMM_ADDR <= (others => '0');
+			R_TMM_DATA <= (others => '0');
 		elsif rising_edge(CLK) then
-			state <= next_state;
+			case state is
+				when PL_BAM_ADDR =>
+					state <= PL_BAM_DATA;
+					R_BAM_ADDR <= T_BAM_ADDR;
+				when PL_BAM_DATA =>
+					state <= PL_TMM_ADDR;
+					R_BAM_DATA <= T_BAM_DATA;
+				when PL_TMM_ADDR =>
+					state <= PL_TMM_DATA;
+					R_TMM_ADDR <= T_TMM_ADDR;
+				when PL_TMM_DATA =>
+					state <= PL_BAM_ADDR;
+					R_TMM_DATA <= T_TMM_DATA;
+			end case;
 		end if;
 	end process;
-
-	-- sync read/write
-	process(state)
-	begin
-		next_state <= state;
-		case state is
-			when PL_BAM_ADDR =>
-				next_state <= PL_BAM_DATA;
-				BAM_ADDR <= O_BAM_ADDR;
-
-			when PL_BAM_DATA =>
-				next_state <= PL_TMM_ADDR;
-				I_BAM_DATA <= BAM_DATA;
-				
-			when PL_TMM_ADDR =>
-				next_state <= PL_TMM_DATA;
-				TMM_ADDR <= O_TMM_ADDR;
-
-			when PL_TMM_DATA =>
-				next_state <= PL_BAM_ADDR;
-				I_TMM_DATA <= TMM_DATA;
-
-				
-		end case;
-	end process;
-
 end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index c79fd58..af6fbe7 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="39"/>
+    <Option Name="WTXSimLaunchSim" Val="42"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -239,6 +239,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -292,11 +300,12 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
-- 
cgit v1.2.3


From b9fa0b2333b4abe62cf19072eb0c38616997bb3c Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Tue, 21 Feb 2023 23:28:31 +0100
Subject: WIP foreground sprite + `std_logic_vector` -> `unsigned` mess

---
 basys3/basys3.srcs/ppu_consts.vhd              | 20 +++---
 basys3/basys3.srcs/ppu_sprite_bg.vhd           | 50 ++++++--------
 basys3/basys3.srcs/ppu_sprite_fg.vhd           | 93 ++++++++++++--------------
 basys3/basys3.srcs/ppu_sprite_transform.vhd    | 16 ++---
 basys3/basys3.srcs/ppu_sprite_transform_tb.vhd | 32 ++++-----
 basys3/basys3.xpr                              | 15 ++---
 6 files changed, 106 insertions(+), 120 deletions(-)

(limited to 'basys3/basys3.srcs/ppu_sprite_bg.vhd')

diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 89b7a7a..722954d 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -2,7 +2,7 @@
 package ppu_consts is
 	constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
-	constant PPU_FG_SPRITE_COUNT : natural := 128; -- amount of foreground sprites
+	constant PPU_FG_SPRITE_COUNT : natural := 128; -- foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
 	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
 	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
@@ -17,18 +17,22 @@ package ppu_consts is
 	constant PPU_PAL_DATA_WIDTH : natural := 12; -- palette memory ram bus data width
 	constant PPU_AUX_ADDR_WIDTH : natural := 1; -- auxiliary memory ram bus address width
 	constant PPU_AUX_DATA_WIDTH : natural := 16; -- auxiliary memory ram bus data width
-	constant PPU_POS_H_WIDTH : natural := 9; -- amount of bits for horizontal screen offset
-	constant PPU_POS_V_WIDTH : natural := 8; -- amount of bits for vertical screen offset
+	constant PPU_POS_H_WIDTH : natural := 9; -- bits for horizontal screen offset
+	constant PPU_POS_V_WIDTH : natural := 8; -- bits for vertical screen offset
 	constant PPU_SPRITE_WIDTH : natural := 16; -- sprite width (pixels)
 	constant PPU_SPRITE_HEIGHT : natural := 16; -- sprite height (pixels)
+	constant PPU_SPRITE_PIDX_WIDTH : natural := 8; -- bits needed to identify horizontal and vertical pixel within sprite
 	constant PPU_SPRITE_POS_H_WIDTH: natural := 4; -- bits needed to identify horizontal pixel within sprite
 	constant PPU_SPRITE_POS_V_WIDTH: natural := 4; -- bits needed to identify vertical pixel within sprite
 	constant PPU_SCREEN_WIDTH : natural := 320; -- absolute screen width (pixels)
 	constant PPU_SCREEN_HEIGHT : natural := 240; -- absolute screen height (pixels)
-	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- amount of tiles (horizontally) on background canvas
-	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- amount of tiles (vertically) on background canvas
-	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- amount of bits needed to index a tile from TMM memory
-	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- amount of pixels defined in one word in TMM memory
-	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- amount of words needed for a single sprite
+	constant PPU_BG_CANVAS_TILES_H : natural := 40; -- tiles (horizontally) on background canvas
+	constant PPU_BG_CANVAS_TILES_V : natural := 30; -- tiles (vertically) on background canvas
+	constant PPU_BG_CANVAS_TILE_H_WIDTH : natural := 6; -- bits needed to describe horizontal bg tile index (grid coordinates)
+	constant PPU_BG_CANVAS_TILE_V_WIDTH : natural := 5; -- bits needed to describe vertical bg tile index (grid coordinates)
+	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- bits needed to index a tile from TMM memory
+	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- pixels defined in one word in TMM memory
+	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- words needed for a single sprite
+	constant PPU_PIXEL_BIT_WIDTH : natural := 3; -- bits needed to identify pixel in TMM word
 end package ppu_consts;
 
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index d8235f5..243fd93 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -31,11 +31,11 @@ end ppu_sprite_bg;
 
 architecture Behavioral of ppu_sprite_bg is
 	component ppu_sprite_transform port(
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
 	-- BAM and TMM in/out temp + registers
@@ -57,11 +57,9 @@ architecture Behavioral of ppu_sprite_bg is
 	-- auxiliary signals (temp variables)
 	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to BG canvas instead of viewport)
 	signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
-	signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
-	signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
-	signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
+	signal TILE_PIDX_X, TRANS_TILE_PIDX_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0) := (others => '0'); -- x position of pixel within tile (local tile coords)
+	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- y position of pixel within tile (local tile coords)
+	signal TRANS_TILE_PIDX : integer := 0; -- index of pixel within tile (reading order)
 	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
 	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
@@ -77,32 +75,28 @@ begin
 	T_CIDX <= BAM_DATA_COL_IDX & TMM_DATA_PAL_IDX;
 
 	-- BAM address calculations
-	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X));
-	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y));
-	TILE_IDX_X <= PIXEL_ABS_X / 16;
-	TILE_IDX_Y <= PIXEL_ABS_Y / 16;
-	TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
-	TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
+	PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(BG_SHIFT_X)); -- pixel position relative to background canvas
+	PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(BG_SHIFT_Y)); -- pixel position relative to background canvas
+	TILE_IDX_X <= PIXEL_ABS_X / 16; -- tile grid index
+	TILE_IDX_Y <= PIXEL_ABS_Y / 16; -- tile grid index
+	TILE_PIDX_X <= to_unsigned(PIXEL_ABS_X - TILE_IDX_X * 16, TILE_PIDX_X'length); -- (sprite local) pixel coords
+	TILE_PIDX_Y <= to_unsigned(PIXEL_ABS_Y - TILE_IDX_Y * 16, TILE_PIDX_Y'length); -- (sprite local) pixel coords
 	T_BAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_BG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_BAM_ADDR_WIDTH));
 
 	-- BAM data dependant calculations
-	TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
-	TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
 	transform: component ppu_sprite_transform port map(
-		XI => TRANSFORM_XI,
-		YI => TRANSFORM_YI,
+		XI => TILE_PIDX_X,
+		YI => TILE_PIDX_Y,
 		FLIP_H => BAM_DATA_FLIP_H,
 		FLIP_V => BAM_DATA_FLIP_V,
-		XO => TRANSFORM_XO,
-		YO => TRANSFORM_YO);
-	TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
-	TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
+		XO => TRANS_TILE_PIDX_X,
+		YO => TRANS_TILE_PIDX_Y);
 
-	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
-
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
+	-- TMM address calculations
+	TRANS_TILE_PIDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
index 340104a..c3cb59a 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -36,11 +36,11 @@ end ppu_sprite_fg;
 
 architecture Behavioral of ppu_sprite_fg is
 	component ppu_sprite_transform port(
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 	component er_ram -- exposed register RAM
 		generic(
@@ -77,15 +77,13 @@ architecture Behavioral of ppu_sprite_fg is
 	alias FAM_REG_COL_IDX is INT_FAM(12 downto 10); -- Palette index for tile
 	alias FAM_REG_TILE_IDX is INT_FAM(9 downto 0); -- Tilemap index
 
-	-- signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to FG canvas instead of viewport)
-	-- signal TILE_IDX_X, TILE_IDX_Y : integer := 0; -- background canvas tile grid xy
-	-- signal TILE_PIXEL_IDX_X, TILE_PIXEL_IDX_Y : integer := 0; -- xy position of pixel within tile (local tile coords)
-	-- signal TRANS_TILE_PIDX_X, TRANS_TILE_PIDX_Y : integer := 0; -- transformed xy position of pixel within tile
-	-- signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
-	-- signal TRANSFORM_XI, TRANSFORM_XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- transform inputs/outputs (x axis)
-	-- signal TRANSFORM_YI, TRANSFORM_YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- transform inputs/outputs (y axis)
-	-- signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
-	-- signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
+	signal SPRITE_ACTIVE : std_logic := '0'; -- is pixel in bounding box of sprite
+	signal PIXEL_ABS_X, PIXEL_ABS_Y : integer := 0; -- absolute pixel position (relative to FG canvas instead of viewport)
+	signal TILE_PIDX_X, TRANS_TILE_PIDX_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
+	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
+	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
+	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
+	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
 begin
 	-- output drivers
@@ -104,42 +102,39 @@ begin
 		DATA => FAM_DATA,
 		REG => INT_FAM);
 
-	-- -- -- FAM address calculations
-	-- -- PIXEL_ABS_X <= to_integer(unsigned(X)) + to_integer(unsigned(FG_SHIFT_X));
-	-- -- PIXEL_ABS_Y <= to_integer(unsigned(Y)) + to_integer(unsigned(FG_SHIFT_Y));
-	-- -- TILE_IDX_X <= PIXEL_ABS_X / 16;
-	-- -- TILE_IDX_Y <= PIXEL_ABS_Y / 16;
-	-- -- TILE_PIXEL_IDX_X <= PIXEL_ABS_X - TILE_IDX_X * 16;
-	-- -- TILE_PIXEL_IDX_Y <= PIXEL_ABS_Y - TILE_IDX_Y * 16;
-	-- -- T_FAM_ADDR <= std_logic_vector(to_unsigned((TILE_IDX_Y * integer(PPU_FG_CANVAS_TILES_H)) + TILE_IDX_X, PPU_FAM_ADDR_WIDTH));
-
-	-- -- -- FAM data dependant calculations
-	-- -- TRANSFORM_XI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_X, PPU_SPRITE_POS_H_WIDTH));
-	-- -- TRANSFORM_YI <= std_logic_vector(to_unsigned(TILE_PIXEL_IDX_Y, PPU_SPRITE_POS_V_WIDTH));
-	-- -- transform: component ppu_sprite_transform port map(
-	-- -- 	XI => TRANSFORM_XI,
-	-- -- 	YI => TRANSFORM_YI,
-	-- -- 	FLIP_H => FAM_DATA_FLIP_H,
-	-- -- 	FLIP_V => FAM_DATA_FLIP_V,
-	-- -- 	XO => TRANSFORM_XO,
-	-- -- 	YO => TRANSFORM_YO);
-	-- -- TRANS_TILE_PIDX_X <= to_integer(unsigned(TRANSFORM_XO));
-	-- -- TRANS_TILE_PIDX_Y <= to_integer(unsigned(TRANSFORM_YO));
-
-	-- -- TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * TRANS_TILE_PIDX_Y + TRANS_TILE_PIDX_X;
-	-- -- TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD;
-	-- -- PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD;
-
-	-- -- T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH));
-
-	-- -- -- TMM DATA
-	-- -- with PIXEL_BIT_OFFSET select
-	-- -- 	TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
-	-- -- 	                    R_TMM_DATA(5 downto 3) when 1,
-	-- -- 	                    R_TMM_DATA(8 downto 6) when 2,
-	-- -- 	                    R_TMM_DATA(11 downto 9) when 3,
-	-- -- 	                    R_TMM_DATA(14 downto 12) when 4,
-	-- -- 	                    (others => '0') when others;
+	SPRITE_ACTIVE <= ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
+									 ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
+	                 ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
+									 ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH)));
+
+	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX); -- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
+
+	TILE_PIDX_X <= to_unsigned(unsigned(X) + 16 - to_unsigned(FAM_REG_POS_H, TILE_PIDX_X'length), TILE_PIDX_X'length); -- (sprite local) pixel coords
+	TILE_PIDX_Y <= to_unsigned(unsigned(Y) + 16 - to_unsigned(FAM_REG_POS_V, TILE_PIDX_Y'length), TILE_PIDX_Y'length); -- (sprite local) pixel coords
+
+	-- FAM data dependant calculations
+	transform: component ppu_sprite_transform port map(
+		XI => TILE_PIDX_X,
+		YI => TILE_PIDX_Y,
+		FLIP_H => FAM_REG_FLIP_H,
+		FLIP_V => FAM_REG_FLIP_V,
+		XO => TRANS_TILE_PIDX_X,
+		YO => TRANS_TILE_PIDX_Y);
+
+	-- TMM address calculations (sprite word start, word offset, and pixel offset)
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
+	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+
+	-- TMM DATA
+	with PIXEL_BIT_OFFSET select
+		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
+		                    R_TMM_DATA(5 downto 3) when 1,
+		                    R_TMM_DATA(8 downto 6) when 2,
+		                    R_TMM_DATA(11 downto 9) when 3,
+		                    R_TMM_DATA(14 downto 12) when 4,
+		                    (others => '0') when others;
 
 	-- state machine (pipeline stage counter) + sync r/w
 	process(CLK, RESET)
diff --git a/basys3/basys3.srcs/ppu_sprite_transform.vhd b/basys3/basys3.srcs/ppu_sprite_transform.vhd
index fa10b9b..f94616c 100644
--- a/basys3/basys3.srcs/ppu_sprite_transform.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_transform.vhd
@@ -5,19 +5,19 @@ use ieee.numeric_std.all;
 use work.ppu_consts.all;
 
 entity ppu_sprite_transform is port( -- flip sprites
-	XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-	YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+	XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+	YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 	FLIP_H, FLIP_V : in std_logic; -- flip sprite
-	XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-	YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+	XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+	YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 end ppu_sprite_transform;
 
 architecture Behavioral of ppu_sprite_transform is
-	signal FLIPPED_X : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal FLIPPED_Y : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal FLIPPED_X : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal FLIPPED_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 begin
-	FLIPPED_X <= std_logic_vector(to_unsigned(PPU_SPRITE_WIDTH-1 - to_integer(unsigned(XI)), PPU_SPRITE_POS_H_WIDTH));
-	FLIPPED_Y <= std_logic_vector(to_unsigned(PPU_SPRITE_HEIGHT-1 - to_integer(unsigned(YI)), PPU_SPRITE_POS_V_WIDTH));
+	FLIPPED_X <= to_unsigned(PPU_SPRITE_WIDTH-1, PPU_SPRITE_POS_H_WIDTH) - XI;
+	FLIPPED_Y <= to_unsigned(PPU_SPRITE_HEIGHT-1, PPU_SPRITE_POS_V_WIDTH) - YI;
 
 	XO <= FLIPPED_X when FLIP_V = '1' else XI;
 	YO <= FLIPPED_Y when FLIP_H = '1' else YI;
diff --git a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
index cec8c20..516a653 100644
--- a/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_transform_tb.vhd
@@ -12,18 +12,18 @@ end ppu_sprite_transform_tb;
 
 architecture behavioral of ppu_sprite_transform_tb is
 	component ppu_sprite_transform port( -- flip sprites
-		XI : in std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
-		YI : in std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
+		XI : in unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- pixel position relative to tile
+		YI : in unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0); -- pixel position relative to tile
 		FLIP_H, FLIP_V : in std_logic; -- flip sprite
-		XO : out std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
-		YO : out std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
+		XO : out unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0); -- new pixel position relative to tile
+		YO : out unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0)); -- new pixel position relative to tile
 	end component;
 
-	signal XI : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal YI : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal XI : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal YI : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 	signal FLIP_H, FLIP_V : std_logic := '0';
-	signal XO : std_logic_vector(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
-	signal YO : std_logic_vector(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
+	signal XO : unsigned(PPU_SPRITE_POS_H_WIDTH-1 downto 0);
+	signal YO : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0);
 begin
 	uut : component ppu_sprite_transform
 		port map(
@@ -36,12 +36,12 @@ begin
 
 	tb : process
 	begin
-		XI <= std_logic_vector(to_unsigned(4, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(4, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(6, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		FLIP_H <= '1';
@@ -50,15 +50,15 @@ begin
 		FLIP_V <= '1';
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(6, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(8, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(6, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(8, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		FLIP_H <= '0';
 		wait for 5 ns;
 
-		XI <= std_logic_vector(to_unsigned(2, PPU_SPRITE_POS_H_WIDTH));
-		YI <= std_logic_vector(to_unsigned(14, PPU_SPRITE_POS_V_WIDTH));
+		XI <= to_unsigned(2, PPU_SPRITE_POS_H_WIDTH);
+		YI <= to_unsigned(14, PPU_SPRITE_POS_V_WIDTH);
 		wait for 5 ns;
 
 		wait; -- stop for simulator
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 7bc2f3c..d828223 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="42"/>
+    <Option Name="WTXSimLaunchSim" Val="55"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -168,7 +168,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu"/>
+        <Option Name="TopModule" Val="ppu_sprite_bg"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -247,18 +247,11 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
-      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedInSteps" Val="synth_1"/>
-          <Attr Name="AutoDcp" Val="1"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -312,7 +305,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu_sprite_bg.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
-- 
cgit v1.2.3


From c09e9faf7e325184e435539d3e06d8340c67acd9 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Wed, 22 Feb 2023 16:13:12 +0100
Subject: WIP ppu fg sprite fetch logic

---
 basys3/basys3.srcs/ppu.vhd           |  25 ++++++--
 basys3/basys3.srcs/ppu_consts.vhd    |  23 ++++++-
 basys3/basys3.srcs/ppu_sprite_bg.vhd |   2 +-
 basys3/basys3.srcs/ppu_sprite_fg.vhd | 120 ++++++++++++++++++++++-------------
 basys3/basys3.xpr                    |  16 +++--
 5 files changed, 126 insertions(+), 60 deletions(-)

(limited to 'basys3/basys3.srcs/ppu_sprite_bg.vhd')

diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 22ee210..61c22aa 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -110,6 +110,7 @@ architecture Behavioral of ppu is
 			X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 			Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 			FETCH : in std_logic; -- fetch sprite data from TMM (TODO : generic map, set foreground sprite component index)
+			VBLANK : in std_logic; -- fetch during vblank
 
 			-- internal memory block (FAM)
 			FAM_WEN : in std_logic; -- VRAM FAM write enable
@@ -188,6 +189,8 @@ architecture Behavioral of ppu is
 	signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
 	signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
 	signal FG_FETCH : std_logic;
+	signal TINY_VBLANK, TINY_VSYNC, TINY_HBLANK, TINY_HSYNC,
+	       NATIVE_VSYNC, NATIVE_HSYNC : std_logic;
 begin
 	SYSCLK <= CLK100;
 	SYSRST <= RESET;
@@ -201,6 +204,13 @@ begin
 	FAM_AI <= (others => '0');
 	PAL_AI <= (others => '0');
 
+	TVBLANK <= TINY_VBLANK;
+	TVSYNC <= TINY_VSYNC;
+	THBLANK <= TINY_HBLANK;
+	THSYNC <= TINY_HSYNC;
+	NVSYNC <= NATIVE_VSYNC;
+	NHSYNC <= NATIVE_HSYNC;
+
 	pipeline_clock_edge_generator : component ppu_pceg port map(
 		CLK => SYSCLK,
 		RESET => SYSRST,
@@ -273,12 +283,13 @@ begin
 		foreground_sprite : component ppu_sprite_fg
 			generic map( IDX => FG_IDX )
 			port map(
-				CLK => PL_SPRITE,
+				CLK => SYSCLK,
 				RESET => SYSRST,
 				OE => FG_EN(FG_IDX),
 				X => X,
 				Y => Y,
 				FETCH => FG_FETCH,
+				VBLANK => TINY_VBLANK,
 				FAM_WEN => FAM_WEN,
 				FAM_ADDR => FAM_AO,
 				FAM_DATA => DATA(PPU_FAM_DATA_WIDTH-1 downto 0),
@@ -323,10 +334,10 @@ begin
 		RESET => SYSRST,
 		X => X,
 		Y => Y,
-		VSYNC => TVSYNC,
-		VBLANK => TVBLANK,
-		HSYNC => THSYNC,
-		HBLANK => THBLANK);
+		VSYNC => TINY_VSYNC,
+		VBLANK => TINY_VBLANK,
+		HSYNC => TINY_HSYNC,
+		HBLANK => TINY_HBLANK);
 
 	native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler)
 		CLK => SYSCLK,
@@ -340,6 +351,6 @@ begin
 		RO => R,
 		GO => G,
 		BO => B,
-		VSYNC => NVSYNC,
-		HSYNC => NHSYNC);
+		VSYNC => NATIVE_VSYNC,
+		HSYNC => NATIVE_HSYNC);
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_consts.vhd b/basys3/basys3.srcs/ppu_consts.vhd
index 722954d..75b6168 100644
--- a/basys3/basys3.srcs/ppu_consts.vhd
+++ b/basys3/basys3.srcs/ppu_consts.vhd
@@ -1,12 +1,18 @@
+library ieee;
+use ieee.math_real.all;
+
 -- https://docs.google.com/spreadsheets/d/1MU6K4c4PtMR_JXIpc3I0ZJdLZNnoFO7G2P3olCz6LSc
 package ppu_consts is
+	-- utility functions
+	function ceil_log2(n : natural) return natural;
+
 	constant PPU_RAM_BUS_ADDR_WIDTH : natural := 16; -- RAM bus address width
 	constant PPU_RAM_BUS_DATA_WIDTH : natural := 16; -- RAM bus data width
 	constant PPU_FG_SPRITE_COUNT : natural := 128; -- foreground sprites
 	constant PPU_COLOR_OUTPUT_DEPTH : natural := 4; -- VGA output channel depth
 	constant PPU_PALETTE_COLOR_WIDTH : natural := 3; -- palette index width (within sprite)
 	constant PPU_PALETTE_INDEX_WIDTH : natural := 3; -- palette index width (palette table)
-	constant PPU_PALETTE_CIDX_WIDTH : natural := PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH; -- global palette index width
+	constant PPU_PALETTE_CIDX_WIDTH : natural := (PPU_PALETTE_COLOR_WIDTH + PPU_PALETTE_INDEX_WIDTH); -- global palette index width
 	constant PPU_TMM_ADDR_WIDTH : natural := 16; -- tilemap memory ram bus address width
 	constant PPU_TMM_DATA_WIDTH : natural := 15; -- tilemap memory ram bus data width
 	constant PPU_BAM_ADDR_WIDTH : natural := 11; -- background attribute memory ram bus address width
@@ -32,7 +38,18 @@ package ppu_consts is
 	constant PPU_BG_CANVAS_TILE_V_WIDTH : natural := 5; -- bits needed to describe vertical bg tile index (grid coordinates)
 	constant PPU_TILE_INDEX_WIDTH : natural := 10; -- bits needed to index a tile from TMM memory
 	constant PPU_PIXELS_PER_TILE_WORD : natural := 5; -- pixels defined in one word in TMM memory
-	constant PPU_SPRITE_PIXELS_PER_WORD : natural := 52; -- words needed for a single sprite
+	constant PPU_SPRITE_WORD_COUNT : natural := 52; -- words needed for a single sprite
 	constant PPU_PIXEL_BIT_WIDTH : natural := 3; -- bits needed to identify pixel in TMM word
+	constant PPU_TILE_BIT_WIDTH : natural := (PPU_SPRITE_WIDTH * PPU_SPRITE_HEIGHT * PPU_PALETTE_COLOR_WIDTH); -- bits in single tile
+	constant PPU_TMM_CACHE_FETCH_C_COUNT : natural := PPU_SPRITE_WORD_COUNT + 1;
+	constant PPU_TMM_CACHE_FETCH_A_COUNT : natural := PPU_TMM_CACHE_FETCH_C_COUNT * PPU_FG_SPRITE_COUNT; -- amount of clocks to fetch new TMM cache
+	constant PPU_TMM_CACHE_FETCH_A_WIDTH : natural := ceil_log2(PPU_TMM_CACHE_FETCH_A_COUNT);
 end package ppu_consts;
-
+package body ppu_consts is
+	-- https://stackoverflow.com/questions/21783280/number-of-bits-to-represent-an-integer-in-vhdl
+	-- Returns number of bits required to represent val in binary vector
+	function ceil_log2(n : natural) return natural is
+	begin
+		return natural(integer(ceil(log2(real(n - 1)))));
+	end function;
+end package body ppu_consts;
diff --git a/basys3/basys3.srcs/ppu_sprite_bg.vhd b/basys3/basys3.srcs/ppu_sprite_bg.vhd
index 243fd93..dba5b8e 100644
--- a/basys3/basys3.srcs/ppu_sprite_bg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_bg.vhd
@@ -96,7 +96,7 @@ begin
 	TRANS_TILE_PIDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
 	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
 	PIXEL_BIT_OFFSET <= TRANS_TILE_PIDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_WORD_COUNT * to_integer(unsigned(BAM_DATA_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
 
 	-- TMM DATA
 	with PIXEL_BIT_OFFSET select
diff --git a/basys3/basys3.srcs/ppu_sprite_fg.vhd b/basys3/basys3.srcs/ppu_sprite_fg.vhd
index c3cb59a..7b39b1d 100644
--- a/basys3/basys3.srcs/ppu_sprite_fg.vhd
+++ b/basys3/basys3.srcs/ppu_sprite_fg.vhd
@@ -19,6 +19,7 @@ entity ppu_sprite_fg is -- foreground sprite
 		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
 		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 		FETCH : in std_logic; -- fetch sprite data from TMM
+		VBLANK : in std_logic; -- fetch during vblank
 
 		-- internal memory block (FAM)
 		FAM_WEN : in std_logic; -- VRAM FAM write enable
@@ -44,10 +45,10 @@ architecture Behavioral of ppu_sprite_fg is
 	end component;
 	component er_ram -- exposed register RAM
 		generic(
-			ADDR_W : natural := PPU_FAM_ADDR_WIDTH; -- ADDR line width
-			DATA_W : natural := PPU_FAM_DATA_WIDTH; -- DATA line width
-			ADDR_LOW : natural := IDX*2; -- starting address
-			ADDR_RANGE : natural := 2); -- amount of valid addresses after ADDR_LOW
+			ADDR_W : natural := 2; -- ADDR line width
+			DATA_W : natural := 2; -- DATA line width
+			ADDR_LOW : natural := 16#0000#; -- starting address
+			ADDR_RANGE : natural := 16#0002#); -- amount of valid addresses after ADDR_LOW
 		port(
 			CLK : in std_logic; -- clock
 			RST : in std_logic; -- async memory clear
@@ -83,8 +84,13 @@ architecture Behavioral of ppu_sprite_fg is
 	signal TILE_PIDX_Y, TRANS_TILE_PIDX_Y : unsigned(PPU_SPRITE_POS_V_WIDTH-1 downto 0) := (others => '0'); -- xy position of pixel within tile (local tile coords)
 	signal TRANS_TILE_PIXEL_IDX : integer := 0; -- index of pixel within tile (reading order)
 	signal TILEMAP_WORD_OFFSET : integer := 0; -- word offset from tile start address in TMM
-	signal PIXEL_BIT_OFFSET : integer := 0; -- pixel index within word of TMM
 	signal TMM_DATA_PAL_IDX : std_logic_vector(PPU_PALETTE_COLOR_WIDTH-1 downto 0); -- color of palette
+
+	-- TMM cache
+	signal TMM_CACHE_WEN : std_logic := '0';
+	signal TMM_CACHE_DATA : std_logic_vector(PPU_TMM_DATA_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_CACHE_ADDR : std_logic_vector(PPU_TMM_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal TMM_CACHE : std_logic_vector((PPU_SPRITE_WORD_COUNT * PPU_TMM_DATA_WIDTH)-1 downto 0);
 begin
 	-- output drivers
 	CIDX <= T_CIDX when OE = '1' else (others => 'Z');
@@ -94,25 +100,31 @@ begin
 	T_CIDX <= FAM_REG_COL_IDX & TMM_DATA_PAL_IDX;
 
 	-- FAM memory
-	FAM : component er_ram port map(
-		CLK => CLK,
-		RST => RESET,
-		WEN => FAM_WEN,
-		ADDR => FAM_ADDR,
-		DATA => FAM_DATA,
-		REG => INT_FAM);
-
-	SPRITE_ACTIVE <= ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
-									 ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
-	                 ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
-									 ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH)));
-
-	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX); -- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
-
-	TILE_PIDX_X <= to_unsigned(unsigned(X) + 16 - to_unsigned(FAM_REG_POS_H, TILE_PIDX_X'length), TILE_PIDX_X'length); -- (sprite local) pixel coords
-	TILE_PIDX_Y <= to_unsigned(unsigned(Y) + 16 - to_unsigned(FAM_REG_POS_V, TILE_PIDX_Y'length), TILE_PIDX_Y'length); -- (sprite local) pixel coords
-
-	-- FAM data dependant calculations
+	FAM : component er_ram
+		generic map(
+			ADDR_W => PPU_FAM_ADDR_WIDTH,
+			DATA_W => PPU_FAM_DATA_WIDTH,
+			ADDR_LOW => IDX*2,
+			ADDR_RANGE => 2)
+		port map(
+			CLK => CLK,
+			RST => RESET,
+			WEN => FAM_WEN,
+			ADDR => FAM_ADDR,
+			DATA => FAM_DATA,
+			REG => INT_FAM);
+
+	-- pixel position within bounding box of sprite
+	SPRITE_ACTIVE <= '1' when ((unsigned(X) + 16) >= unsigned(FAM_REG_POS_H)) and
+	                          ((unsigned(X) + 16) < (unsigned(FAM_REG_POS_H) + to_unsigned(PPU_SPRITE_WIDTH, PPU_POS_H_WIDTH))) and
+	                          ((unsigned(Y) + 16) >= unsigned(FAM_REG_POS_V)) and
+	                          ((unsigned(Y) + 16) < (unsigned(FAM_REG_POS_V) + to_unsigned(PPU_SPRITE_HEIGHT, PPU_POS_V_WIDTH))) else '0';
+
+	-- (sprite local) pixel coords
+	TILE_PIDX_X <= resize(unsigned(X) + 16 - resize(unsigned(FAM_REG_POS_H), TILE_PIDX_X'length), TILE_PIDX_X'length);
+	TILE_PIDX_Y <= resize(unsigned(Y) + 16 - resize(unsigned(FAM_REG_POS_V), TILE_PIDX_Y'length), TILE_PIDX_Y'length);
+
+	-- transform local coords
 	transform: component ppu_sprite_transform port map(
 		XI => TILE_PIDX_X,
 		YI => TILE_PIDX_Y,
@@ -121,23 +133,39 @@ begin
 		XO => TRANS_TILE_PIDX_X,
 		YO => TRANS_TILE_PIDX_Y);
 
-	-- TMM address calculations (sprite word start, word offset, and pixel offset)
-	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X); -- pixel index of sprite
+	-- pixel index
+	TRANS_TILE_PIXEL_IDX <= integer(PPU_SPRITE_WIDTH) * to_integer(TRANS_TILE_PIDX_Y) + to_integer(TRANS_TILE_PIDX_X);
+	-- palette color at pixel
+	TMM_DATA_PAL_IDX <= TMM_CACHE(TRANS_TILE_PIXEL_IDX * integer(PPU_PALETTE_COLOR_WIDTH) + integer(PPU_PALETTE_COLOR_WIDTH)-1 downto TRANS_TILE_PIXEL_IDX * integer(PPU_PALETTE_COLOR_WIDTH));
+	-- if pixel in sprite hitbox and TMM_DATA_PAL_IDX > 0
+	HIT <= SPRITE_ACTIVE and (nor TMM_DATA_PAL_IDX);
+
+	-- FETCH LOGIC BELOW
+
+	-- TTM cache
+	ttm_cache : component er_ram
+		generic map(
+			ADDR_W => PPU_TMM_ADDR_WIDTH,
+			DATA_W => PPU_TMM_DATA_WIDTH,
+			ADDR_LOW => 0,
+			ADDR_RANGE => PPU_SPRITE_WORD_COUNT)
+		port map(
+			CLK => CLK,
+			RST => RESET,
+			WEN => TMM_CACHE_WEN,
+			ADDR => TMM_CACHE_ADDR,
+			DATA => TMM_CACHE_DATA,
+			REG => TMM_CACHE);
+
 	TILEMAP_WORD_OFFSET <= TRANS_TILE_PIXEL_IDX / PPU_PIXELS_PER_TILE_WORD; -- word offset from starting word of sprite
-	PIXEL_BIT_OFFSET <= TRANS_TILE_PIXEL_IDX mod PPU_PIXELS_PER_TILE_WORD; -- pixel bit offset
-	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_PIXELS_PER_WORD * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
-
-	-- TMM DATA
-	with PIXEL_BIT_OFFSET select
-		TMM_DATA_PAL_IDX <= R_TMM_DATA(2 downto 0) when 0,
-		                    R_TMM_DATA(5 downto 3) when 1,
-		                    R_TMM_DATA(8 downto 6) when 2,
-		                    R_TMM_DATA(11 downto 9) when 3,
-		                    R_TMM_DATA(14 downto 12) when 4,
-		                    (others => '0') when others;
+	T_TMM_ADDR <= std_logic_vector(to_unsigned(PPU_SPRITE_WORD_COUNT * to_integer(unsigned(FAM_REG_TILE_IDX)) + TILEMAP_WORD_OFFSET, PPU_TMM_ADDR_WIDTH)); -- TMM address
+
 
 	-- state machine (pipeline stage counter) + sync r/w
 	process(CLK, RESET)
+		constant TMM_FETCH_CLK_RANGE_BEGIN : natural := PPU_TMM_CACHE_FETCH_C_COUNT * IDX;
+		variable TMM_FETCH_CTR : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
+		variable TMM_FETCH_CTR_REL : unsigned(PPU_TMM_CACHE_FETCH_A_WIDTH-1 downto 0) := (others => '0');
 	begin
 		if RESET = '1' then
 			-- reset state
@@ -146,14 +174,16 @@ begin
 			R_TMM_ADDR <= (others => '0');
 			R_TMM_DATA <= (others => '0');
 		elsif rising_edge(CLK) then
-			case state is
-				when PL_TMM_ADDR =>
-					state <= PL_TMM_DATA;
-					R_TMM_ADDR <= T_TMM_ADDR;
-				when PL_TMM_DATA =>
-					state <= PL_TMM_ADDR;
-					R_TMM_DATA <= T_TMM_DATA;
-			end case;
+			TMM_FETCH_CTR := (others => '0') when FETCH = '0' else TMM_FETCH_CTR + 1;
+			TMM_FETCH_CTR_REL := TMM_FETCH_CTR - TMM_FETCH_CLK_RANGE_BEGIN;
+
+			if FETCH = '1' and TMM_FETCH_CTR >= TMM_FETCH_CLK_RANGE_BEGIN and TMM_FETCH_CTR < (TMM_FETCH_CLK_RANGE_BEGIN + PPU_TMM_CACHE_FETCH_C_COUNT) then
+				TMM_CACHE_WEN <= '1';
+				R_TMM_DATA <= T_TMM_DATA;
+				T_TMM_ADDR <= R_TMM_ADDR;
+			else
+				TMM_CACHE_WEN <= '0';
+			end if;
 		end if;
 	end process;
 end Behavioral;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index d828223..813b3e2 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="55"/>
+    <Option Name="WTXSimLaunchSim" Val="57"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -168,7 +168,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_bg"/>
+        <Option Name="TopModule" Val="ppu"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -237,7 +237,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
+        <Option Name="TopModule" Val="er_ram_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -252,6 +252,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -305,7 +313,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="19">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ppu.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
         <Step Id="synth_design"/>
-- 
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