From 9f38ab7fd66698c43b78b508eebc85730ba114b8 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Wed, 29 Mar 2023 17:42:07 +0200 Subject: update pipeline --- basys3/basys3.srcs/ppu_dispctl.vhd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'basys3/basys3.srcs/ppu_dispctl.vhd') diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd index 1d3d922..4f017f3 100644 --- a/basys3/basys3.srcs/ppu_dispctl.vhd +++ b/basys3/basys3.srcs/ppu_dispctl.vhd @@ -15,7 +15,8 @@ entity ppu_dispctl is port( RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out NVSYNC, NHSYNC : out std_logic; -- VGA sync out - THBLANK, TVBLANK : out std_logic); -- tiny sync signals + THBLANK, TVBLANK : out std_logic; -- tiny sync signals + ACTIVE : out std_logic); -- screen currently active (currently same for tiny/native, TODO: offset tiny for first scanline) end ppu_dispctl; architecture Behavioral of ppu_dispctl is @@ -145,6 +146,7 @@ begin if TMP_NHCOUNT = PPU_VGA_H_PORCH_BACK + PPU_VGA_H_ACTIVE + PPU_VGA_H_SYNC then TMP_NHSYNC := '0'; end if; end if; end process; + ACTIVE <= NACTIVE; scanline_buffer : component ppu_dispctl_slbuf port map( clka => SYSCLK, -- cgit v1.2.3