From 0c23afa5651cc3d7f9ad53311446325e35313347 Mon Sep 17 00:00:00 2001 From: lonkaars Date: Mon, 20 Mar 2023 17:04:33 +0100 Subject: debugged the ppu (still WIP, but some output is visible) --- basys3/basys3.srcs/ppu_dispctl.vhd | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'basys3/basys3.srcs/ppu_dispctl.vhd') diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd index 117b780..1d3d922 100644 --- a/basys3/basys3.srcs/ppu_dispctl.vhd +++ b/basys3/basys3.srcs/ppu_dispctl.vhd @@ -20,10 +20,10 @@ end ppu_dispctl; architecture Behavioral of ppu_dispctl is component ppu_dispctl_pixclk is port ( - clk_out1 : out std_logic; - clk_out2 : out std_logic; + npxclk : out std_logic; + tpxclk : out std_logic; reset : in std_logic; - clk_in1 : in std_logic); + sysclk : in std_logic); end component; component ppu_dispctl_slbuf port( -- scanline buffer clka : in std_logic; @@ -159,8 +159,8 @@ begin rstb_busy => open); pixel_clock: component ppu_dispctl_pixclk port map( - clk_in1 => SYSCLK, + sysclk => SYSCLK, reset => RESET, - clk_out1 => NPIXCLK, - clk_out2 => TPIXCLK); + npxclk => NPIXCLK, + tpxclk => TPIXCLK); end Behavioral; -- cgit v1.2.3