From f866622276090889e16e117add53384a98c4a9a7 Mon Sep 17 00:00:00 2001 From: UnavailableDev Date: Sun, 19 Feb 2023 12:31:16 +0100 Subject: apu note 2 freq --- basys3/basys3.srcs/apu_tb_note_to_frequency.vhd | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 basys3/basys3.srcs/apu_tb_note_to_frequency.vhd (limited to 'basys3/basys3.srcs/apu_tb_note_to_frequency.vhd') diff --git a/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd b/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd new file mode 100644 index 0000000..385071e --- /dev/null +++ b/basys3/basys3.srcs/apu_tb_note_to_frequency.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity apu_tb_note_to_frequency is +end entity; + +architecture Behavioral of apu_tb_note_to_frequency is + + component apu_note_to_frequency is + port ( + data : in std_logic_vector(7 downto 0); + freq : out std_logic_vector(11 downto 0) --frequency + ); + end component; + + signal data : std_logic_vector(7 downto 0) := (others => '0'); + signal freq : std_logic_vector(11 downto 0) := (others => '0'); + + signal OK : boolean := false; + +begin + UUT: apu_note_to_frequency + port map ( + data => data, + freq => freq + ); + + TB: process + begin + for I in 0 to 255 loop + data <= std_logic_vector(to_unsigned(I, 8)); + wait for 4 ps; + end loop; + end process; + +end architecture; \ No newline at end of file -- cgit v1.2.3