From e608ff1230b1db80cb4d68e513fb05fc92774bdc Mon Sep 17 00:00:00 2001 From: lonkaars Date: Mon, 20 Feb 2023 12:39:43 +0100 Subject: update code style --- basys3/basys3.srcs/apu_note_to_frequency_tb.vhd | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'basys3/basys3.srcs/apu_note_to_frequency_tb.vhd') diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd index 6814c1f..f48a40c 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd @@ -10,20 +10,20 @@ end entity; architecture Behavioral of apu_note_to_frequency_tb is component apu_note_to_frequency is port( - data: in std_logic_vector(7 downto 0); - freq: out std_logic_vector(11 downto 0)); -- frequency + data : in std_logic_vector(7 downto 0); + freq : out std_logic_vector(11 downto 0)); -- frequency end component; - signal data: std_logic_vector(7 downto 0) := (others => '0'); - signal freq: std_logic_vector(11 downto 0) := (others => '0'); + signal data : std_logic_vector(7 downto 0) := (others => '0'); + signal freq : std_logic_vector(11 downto 0) := (others => '0'); - signal ok: boolean := false; + signal ok : boolean := false; begin - uut: apu_note_to_frequency port map( + uut : apu_note_to_frequency port map( data => data, freq => freq); - tb: process + tb : process begin for i in 0 to 255 loop data <= std_logic_vector(to_unsigned(i, 8)); -- cgit v1.2.3