From 9b84c25a53b7269228743e398b13c19af505226b Mon Sep 17 00:00:00 2001 From: lonkaars Date: Sun, 19 Feb 2023 14:26:49 +0100 Subject: format and add apu sources to vivado project file --- basys3/basys3.srcs/apu_note_to_frequency_tb.vhd | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 basys3/basys3.srcs/apu_note_to_frequency_tb.vhd (limited to 'basys3/basys3.srcs/apu_note_to_frequency_tb.vhd') diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd new file mode 100644 index 0000000..6814c1f --- /dev/null +++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity apu_note_to_frequency_tb is +end entity; + +architecture Behavioral of apu_note_to_frequency_tb is + component apu_note_to_frequency is port( + data: in std_logic_vector(7 downto 0); + freq: out std_logic_vector(11 downto 0)); -- frequency + end component; + + signal data: std_logic_vector(7 downto 0) := (others => '0'); + signal freq: std_logic_vector(11 downto 0) := (others => '0'); + + signal ok: boolean := false; +begin + uut: apu_note_to_frequency port map( + data => data, + freq => freq); + + tb: process + begin + for i in 0 to 255 loop + data <= std_logic_vector(to_unsigned(i, 8)); + wait for 4 ps; + end loop; + end process; +end architecture; -- cgit v1.2.3