From 97990bc21cdd391b06dda72c0cf2f2e93b6867dc Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Fri, 3 Mar 2023 12:29:47 +0100
Subject: fix apu_note_to_frequency

---
 basys3/basys3.srcs/apu_note_to_frequency.vhd    |  5 +--
 basys3/basys3.srcs/apu_note_to_frequency_tb.vhd |  6 ++--
 basys3/basys3.xpr                               | 46 +++++++++++++++----------
 3 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 48defa3..17c396c 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
 library work;
@@ -13,7 +14,7 @@ entity apu_note_to_frequency is port (
 end entity;
 
 architecture Behavioral of apu_note_to_frequency is
-	signal buff : std_logic_vector(15 downto 0) := (others => '0');
+	signal buff : std_logic_vector(11 downto 0) := (others => '0');
 	signal shift : integer;
 begin
 
@@ -34,6 +35,6 @@ begin
         x"100" when data(6 downto 3) = (x"C") else -- B     256
         x"000";
 
-    freq <= std_logic_vector( shift_right(unsigned(buff), natural(shift)) ); -- TODO: MAYBE WORKY???
+    freq <= std_logic_vector(shift_right(unsigned(buff), shift)); -- TODO: MAYBE WORKY???
 
 end architecture;
diff --git a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
index f48a40c..d7a611a 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency_tb.vhd
@@ -10,11 +10,11 @@ end entity;
 
 architecture Behavioral of apu_note_to_frequency_tb is
 	component apu_note_to_frequency is port(
-		data : in std_logic_vector(7 downto 0);
+		data : in std_logic_vector(6 downto 0);
 		freq : out std_logic_vector(11 downto 0)); -- frequency
 	end component;
 
-	signal data : std_logic_vector(7 downto 0) := (others => '0');
+	signal data : std_logic_vector(6 downto 0) := (others => '0');
 	signal freq : std_logic_vector(11 downto 0) := (others => '0');
 
 	signal ok : boolean := false;
@@ -26,7 +26,7 @@ begin
 	tb : process
 	begin
 		for i in 0 to 255 loop
-			data <= std_logic_vector(to_unsigned(i, 8));
+			data <= std_logic_vector(to_unsigned(i, 7));
 			wait for 4 ps;
 		end loop;
 	end process;
diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr
index 4060a21..7b2c82c 100644
--- a/basys3/basys3.xpr
+++ b/basys3/basys3.xpr
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="113"/>
+    <Option Name="WTXSimLaunchSim" Val="119"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -116,20 +116,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/apu.vhd">
-        <FileInfo>
-          <Attr Name="UserDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/apu_note_to_frequency.vhd">
-        <FileInfo>
-          <Attr Name="UserDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/er_ram.vhd">
         <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -190,6 +176,25 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/apu_consts.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/apu.vhd">
+        <FileInfo>
+          <Attr Name="UserDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/apu_note_to_frequency.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/apu_lut_reader.vhd">
         <FileInfo>
           <Attr Name="UserDisabled" Val="1"/>
@@ -199,7 +204,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu"/>
+        <Option Name="TopModule" Val="apu_note_to_frequency"/>
         <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
@@ -225,7 +230,6 @@
       </File>
       <File Path="$PSRCDIR/apu_note_to_frequency_tb.vhd">
         <FileInfo>
-          <Attr Name="UserDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -266,9 +270,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/apu_lut_reader_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ppu_sprite_fg_tb"/>
+        <Option Name="TopModule" Val="apu_note_to_frequency_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
-- 
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